include/asm/mmu-arcv2.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2004, 2007-2010, 2011-2012, 2019-20 Synopsys, Inc. (www.synopsys.com)
0004  *
0005  * MMUv3 (arc700) / MMUv4 (archs) are software page walked and software managed.
0006  * This file contains the TLB access registers and commands
0007  */
0008
0009 #ifndef _ASM_ARC_MMU_ARCV2_H
0010 #define _ASM_ARC_MMU_ARCV2_H
0011
0012 /*
0013  * TLB Management regs
0014  */
0015 #define ARC_REG_MMU_BCR     0x06f
0016
0017 #ifdef CONFIG_ARC_MMU_V3
0018 #define ARC_REG_TLBPD0      0x405
0019 #define ARC_REG_TLBPD1      0x406
0020 #define ARC_REG_TLBPD1HI    0   /* Dummy: allows common code */
0021 #define ARC_REG_TLBINDEX    0x407
0022 #define ARC_REG_TLBCOMMAND  0x408
0023 #define ARC_REG_PID     0x409
0024 #define ARC_REG_SCRATCH_DATA0   0x418
0025 #else
0026 #define ARC_REG_TLBPD0      0x460
0027 #define ARC_REG_TLBPD1      0x461
0028 #define ARC_REG_TLBPD1HI    0x463
0029 #define ARC_REG_TLBINDEX    0x464
0030 #define ARC_REG_TLBCOMMAND  0x465
0031 #define ARC_REG_PID     0x468
0032 #define ARC_REG_SCRATCH_DATA0   0x46c
0033 #endif
0034
0035 /* Bits in MMU PID reg */
0036 #define __TLB_ENABLE        (1 << 31)
0037 #define __PROG_ENABLE       (1 << 30)
0038 #define MMU_ENABLE      (__TLB_ENABLE | __PROG_ENABLE)
0039
0040 /* Bits in TLB Index reg */
0041 #define TLB_LKUP_ERR        0x80000000
0042
0043 #ifdef CONFIG_ARC_MMU_V3
0044 #define TLB_DUP_ERR     (TLB_LKUP_ERR | 0x00000001)
0045 #else
0046 #define TLB_DUP_ERR     (TLB_LKUP_ERR | 0x40000000)
0047 #endif
0048
0049 /*
0050  * TLB Commands
0051  */
0052 #define TLBWrite            0x1
0053 #define TLBRead             0x2
0054 #define TLBGetIndex         0x3
0055 #define TLBProbe            0x4
0056 #define TLBWriteNI      0x5  /* write JTLB without inv uTLBs */
0057 #define TLBIVUTLB       0x6  /* explicitly inv uTLBs */
0058
0059 #ifdef CONFIG_ARC_MMU_V4
0060 #define TLBInsertEntry      0x7
0061 #define TLBDeleteEntry      0x8
0062 #endif
0063
0064 /* Masks for actual TLB "PD"s */
0065 #define PTE_BITS_IN_PD0     (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ)
0066 #define PTE_BITS_RWX        (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
0067
0068 #define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS | _PAGE_CACHEABLE)
0069
0070 #ifndef __ASSEMBLY__
0071
0072 struct mm_struct;
0073 extern int pae40_exist_but_not_enab(void);
0074
0075 static inline int is_pae40_enabled(void)
0076 {
0077     return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
0078 }
0079
0080 static inline void mmu_setup_asid(struct mm_struct *mm, unsigned long asid)
0081 {
0082     write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
0083 }
0084
0085 static inline void mmu_setup_pgd(struct mm_struct *mm, void *pgd)
0086 {
0087     /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
0088 #ifdef CONFIG_ISA_ARCV2
0089     write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);
0090 #endif
0091 }
0092
0093 #else
0094
0095 .macro ARC_MMU_REENABLE reg
0096     lr \reg, [ARC_REG_PID]
0097     or \reg, \reg, MMU_ENABLE
0098     sr \reg, [ARC_REG_PID]
0099 .endm
0100
0101 #endif /* !__ASSEMBLY__ */
0102
0103 #endif