include/asm/irqflags-compact.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
0004  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0005  */
0006
0007 #ifndef __ASM_IRQFLAGS_ARCOMPACT_H
0008 #define __ASM_IRQFLAGS_ARCOMPACT_H
0009
0010 /* vineetg: March 2010 : local_irq_save( ) optimisation
0011  *  -Remove explicit mov of current status32 into reg, that is not needed
0012  *  -Use BIC  insn instead of INVERTED + AND
0013  *  -Conditionally disable interrupts (if they are not enabled, don't disable)
0014 */
0015
0016 #include <asm/arcregs.h>
0017
0018 /* status32 Reg bits related to Interrupt Handling */
0019 #define STATUS_E1_BIT       1   /* Int 1 enable */
0020 #define STATUS_E2_BIT       2   /* Int 2 enable */
0021 #define STATUS_A1_BIT       3   /* Int 1 active */
0022 #define STATUS_A2_BIT       4   /* Int 2 active */
0023 #define STATUS_AE_BIT       5   /* Exception active */
0024
0025 #define STATUS_E1_MASK      (1<<STATUS_E1_BIT)
0026 #define STATUS_E2_MASK      (1<<STATUS_E2_BIT)
0027 #define STATUS_A1_MASK      (1<<STATUS_A1_BIT)
0028 #define STATUS_A2_MASK      (1<<STATUS_A2_BIT)
0029 #define STATUS_AE_MASK      (1<<STATUS_AE_BIT)
0030 #define STATUS_IE_MASK      (STATUS_E1_MASK | STATUS_E2_MASK)
0031
0032 /* Other Interrupt Handling related Aux regs */
0033 #define AUX_IRQ_LEV     0x200   /* IRQ Priority: L1 or L2 */
0034 #define AUX_IRQ_HINT        0x201   /* For generating Soft Interrupts */
0035 #define AUX_IRQ_LV12        0x43    /* interrupt level register */
0036
0037 #define AUX_IENABLE     0x40c
0038 #define AUX_ITRIGGER        0x40d
0039 #define AUX_IPULSE      0x415
0040
0041 #define ISA_INIT_STATUS_BITS    STATUS_IE_MASK
0042
0043 #ifndef __ASSEMBLY__
0044
0045 /******************************************************************
0046  * IRQ Control Macros
0047  *
0048  * All of them have "memory" clobber (compiler barrier) which is needed to
0049  * ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
0050  * are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
0051  *
0052  * Noted at the time of Abilis Timer List corruption
0053  *
0054  * Orig Bug + Rejected solution:
0055  * https://lore.kernel.org/lkml/1364553218-31255-1-git-send-email-vgupta@synopsys.com
0056  *
0057  * Reasoning:
0058  * https://lore.kernel.org/lkml/CA+55aFyFWjpSVQM6M266tKrG_ZXJzZ-nYejpmXYQXbrr42mGPQ@mail.gmail.com
0059  *
0060  ******************************************************************/
0061
0062 /*
0063  * Save IRQ state and disable IRQs
0064  */
0065 static inline long arch_local_irq_save(void)
0066 {
0067     unsigned long temp, flags;
0068
0069     __asm__ __volatile__(
0070     "   lr  %1, [status32]  \n"
0071     "   bic %0, %1, %2      \n"
0072     "   and.f 0, %1, %2 \n"
0073     "   flag.nz %0      \n"
0074     : "=r"(temp), "=r"(flags)
0075     : "n"((STATUS_E1_MASK | STATUS_E2_MASK))
0076     : "memory", "cc");
0077
0078     return flags;
0079 }
0080
0081 /*
0082  * restore saved IRQ state
0083  */
0084 static inline void arch_local_irq_restore(unsigned long flags)
0085 {
0086
0087     __asm__ __volatile__(
0088     "   flag %0         \n"
0089     :
0090     : "r"(flags)
0091     : "memory");
0092 }
0093
0094 /*
0095  * Unconditionally Enable IRQs
0096  */
0097 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
0098 extern void arch_local_irq_enable(void);
0099 #else
0100 static inline void arch_local_irq_enable(void)
0101 {
0102     unsigned long temp;
0103
0104     __asm__ __volatile__(
0105     "   lr   %0, [status32] \n"
0106     "   or   %0, %0, %1     \n"
0107     "   flag %0         \n"
0108     : "=&r"(temp)
0109     : "n"((STATUS_E1_MASK | STATUS_E2_MASK))
0110     : "cc", "memory");
0111 }
0112 #endif
0113
0114 /*
0115  * Unconditionally Disable IRQs
0116  */
0117 static inline void arch_local_irq_disable(void)
0118 {
0119     unsigned long temp;
0120
0121     __asm__ __volatile__(
0122     "   lr  %0, [status32]  \n"
0123     "   and %0, %0, %1      \n"
0124     "   flag %0         \n"
0125     : "=&r"(temp)
0126     : "n"(~(STATUS_E1_MASK | STATUS_E2_MASK))
0127     : "memory");
0128 }
0129
0130 /*
0131  * save IRQ state
0132  */
0133 static inline long arch_local_save_flags(void)
0134 {
0135     unsigned long temp;
0136
0137     __asm__ __volatile__(
0138     "   lr  %0, [status32]  \n"
0139     : "=&r"(temp)
0140     :
0141     : "memory");
0142
0143     return temp;
0144 }
0145
0146 /*
0147  * Query IRQ state
0148  */
0149 static inline int arch_irqs_disabled_flags(unsigned long flags)
0150 {
0151     return !(flags & (STATUS_E1_MASK
0152 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
0153             | STATUS_E2_MASK
0154 #endif
0155         ));
0156 }
0157
0158 static inline int arch_irqs_disabled(void)
0159 {
0160     return arch_irqs_disabled_flags(arch_local_save_flags());
0161 }
0162
0163 #else
0164
0165 #ifdef CONFIG_TRACE_IRQFLAGS
0166
0167 .macro TRACE_ASM_IRQ_DISABLE
0168     bl  trace_hardirqs_off
0169 .endm
0170
0171 .macro TRACE_ASM_IRQ_ENABLE
0172     bl  trace_hardirqs_on
0173 .endm
0174
0175 #else
0176
0177 .macro TRACE_ASM_IRQ_DISABLE
0178 .endm
0179
0180 .macro TRACE_ASM_IRQ_ENABLE
0181 .endm
0182
0183 #endif
0184
0185 .macro IRQ_DISABLE  scratch
0186     lr  \scratch, [status32]
0187     bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
0188     flag    \scratch
0189     TRACE_ASM_IRQ_DISABLE
0190 .endm
0191
0192 .macro IRQ_ENABLE  scratch
0193     TRACE_ASM_IRQ_ENABLE
0194     lr  \scratch, [status32]
0195     or  \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
0196     flag    \scratch
0197 .endm
0198
0199 #endif  /* __ASSEMBLY__ */
0200
0201 #endif