include/asm/disasm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * several functions that help interpret ARC instructions
0004  * used for unaligned accesses, kprobes and kgdb
0005  *
0006  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0007  */
0008
0009 #ifndef __ARC_DISASM_H__
0010 #define __ARC_DISASM_H__
0011
0012 enum {
0013     op_Bcc = 0, op_BLcc = 1, op_LD = 2, op_ST = 3, op_MAJOR_4 = 4,
0014     op_MAJOR_5 = 5, op_LD_ADD = 12, op_ADD_SUB_SHIFT = 13,
0015     op_ADD_MOV_CMP = 14, op_S = 15, op_LD_S = 16, op_LDB_S = 17,
0016     op_LDW_S = 18, op_LDWX_S = 19, op_ST_S = 20, op_STB_S = 21,
0017     op_STW_S = 22, op_Su5 = 23, op_SP = 24, op_GP = 25,
0018     op_Pcl = 26, op_MOV_S = 27, op_ADD_CMP = 28, op_BR_S = 29,
0019     op_B_S = 30, op_BL_S = 31
0020 };
0021
0022 enum flow {
0023     noflow,
0024     direct_jump,
0025     direct_call,
0026     indirect_jump,
0027     indirect_call,
0028     invalid_instr
0029 };
0030
0031 #define IS_BIT(word, n)     ((word) & (1<<n))
0032 #define BITS(word, s, e)    (((word) >> (s)) & (~((-2) << ((e) - (s)))))
0033
0034 #define MAJOR_OPCODE(word)  (BITS((word), 27, 31))
0035 #define MINOR_OPCODE(word)  (BITS((word), 16, 21))
0036 #define FIELD_A(word)       (BITS((word), 0, 5))
0037 #define FIELD_B(word)       ((BITS((word), 12, 14)<<3) | \
0038                 (BITS((word), 24, 26)))
0039 #define FIELD_C(word)       (BITS((word), 6, 11))
0040 #define FIELD_u6(word)      FIELDC(word)
0041 #define FIELD_s12(word)     sign_extend(((BITS((word), 0, 5) << 6) | \
0042                     BITS((word), 6, 11)), 12)
0043
0044 /* note that for BL/BRcc these two macro's need another AND statement to mask
0045  * out bit 1 (make the result a multiple of 4) */
0046 #define FIELD_s9(word)      sign_extend(((BITS(word, 15, 15) << 8) | \
0047                     BITS(word, 16, 23)), 9)
0048 #define FIELD_s21(word)     sign_extend(((BITS(word, 6, 15) << 11) | \
0049                     (BITS(word, 17, 26) << 1)), 12)
0050 #define FIELD_s25(word)     sign_extend(((BITS(word, 0, 3) << 21) | \
0051                     (BITS(word, 6, 15) << 11) | \
0052                     (BITS(word, 17, 26) << 1)), 12)
0053
0054 /* note: these operate on 16 bits! */
0055 #define FIELD_S_A(word)     ((BITS((word), 2, 2)<<3) | BITS((word), 0, 2))
0056 #define FIELD_S_B(word)     ((BITS((word), 10, 10)<<3) | \
0057                 BITS((word), 8, 10))
0058 #define FIELD_S_C(word)     ((BITS((word), 7, 7)<<3) | BITS((word), 5, 7))
0059 #define FIELD_S_H(word)     ((BITS((word), 0, 2)<<3) | BITS((word), 5, 8))
0060 #define FIELD_S_u5(word)    (BITS((word), 0, 4))
0061 #define FIELD_S_u6(word)    (BITS((word), 0, 4) << 1)
0062 #define FIELD_S_u7(word)    (BITS((word), 0, 4) << 2)
0063 #define FIELD_S_u10(word)   (BITS((word), 0, 7) << 2)
0064 #define FIELD_S_s7(word)    sign_extend(BITS((word), 0, 5) << 1, 9)
0065 #define FIELD_S_s8(word)    sign_extend(BITS((word), 0, 7) << 1, 9)
0066 #define FIELD_S_s9(word)    sign_extend(BITS((word), 0, 8), 9)
0067 #define FIELD_S_s10(word)   sign_extend(BITS((word), 0, 8) << 1, 10)
0068 #define FIELD_S_s11(word)   sign_extend(BITS((word), 0, 8) << 2, 11)
0069 #define FIELD_S_s13(word)   sign_extend(BITS((word), 0, 10) << 2, 13)
0070
0071 #define STATUS32_L      0x00000100
0072 #define REG_LIMM        62
0073
0074 struct disasm_state {
0075     /* generic info */
0076     unsigned long words[2];
0077     int instr_len;
0078     int major_opcode;
0079     /* info for branch/jump */
0080     int is_branch;
0081     int target;
0082     int delay_slot;
0083     enum flow flow;
0084     /* info for load/store */
0085     int src1, src2, src3, dest, wb_reg;
0086     int zz, aa, x, pref, di;
0087     int fault, write;
0088 };
0089
0090 static inline int sign_extend(int value, int bits)
0091 {
0092     if (IS_BIT(value, (bits - 1)))
0093         value |= (0xffffffff << bits);
0094
0095     return value;
0096 }
0097
0098 static inline int is_short_instr(unsigned long addr)
0099 {
0100     uint16_t word = *((uint16_t *)addr);
0101     int opcode = (word >> 11) & 0x1F;
0102     return (opcode >= 0x0B);
0103 }
0104
0105 void disasm_instr(unsigned long addr, struct disasm_state *state,
0106     int userspace, struct pt_regs *regs, struct callee_regs *cregs);
0107 int disasm_next_pc(unsigned long pc, struct pt_regs *regs, struct callee_regs
0108     *cregs, unsigned long *fall_thru, unsigned long *target);
0109 long get_reg(int reg, struct pt_regs *regs, struct callee_regs *cregs);
0110 void set_reg(int reg, long val, struct pt_regs *regs,
0111         struct callee_regs *cregs);
0112
0113 #endif  /* __ARC_DISASM_H__ */