include/asm/cache.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0004  */
0005
0006 #ifndef __ARC_ASM_CACHE_H
0007 #define __ARC_ASM_CACHE_H
0008
0009 /* In case $$ not config, setup a dummy number for rest of kernel */
0010 #ifndef CONFIG_ARC_CACHE_LINE_SHIFT
0011 #define L1_CACHE_SHIFT      6
0012 #else
0013 #define L1_CACHE_SHIFT      CONFIG_ARC_CACHE_LINE_SHIFT
0014 #endif
0015
0016 #define L1_CACHE_BYTES      (1 << L1_CACHE_SHIFT)
0017 #define CACHE_LINE_MASK     (~(L1_CACHE_BYTES - 1))
0018
0019 /*
0020  * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
0021  * Ideal for wiring memory mapped peripherals as we don't need to do
0022  * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
0023  */
0024 #define ARC_UNCACHED_ADDR_SPACE 0xc0000000
0025
0026 #ifndef __ASSEMBLY__
0027
0028 #include <linux/build_bug.h>
0029
0030 /* Uncached access macros */
0031 #define arc_read_uncached_32(ptr)   \
0032 ({                  \
0033     unsigned int __ret;     \
0034     __asm__ __volatile__(       \
0035     "   ld.di %0, [%1]  \n" \
0036     : "=r"(__ret)           \
0037     : "r"(ptr));            \
0038     __ret;              \
0039 })
0040
0041 #define arc_write_uncached_32(ptr, data)\
0042 ({                  \
0043     __asm__ __volatile__(       \
0044     "   st.di %0, [%1]  \n" \
0045     :               \
0046     : "r"(data), "r"(ptr));     \
0047 })
0048
0049 /* Largest line length for either L1 or L2 is 128 bytes */
0050 #define SMP_CACHE_BYTES     128
0051 #define cache_line_size()   SMP_CACHE_BYTES
0052 #define ARCH_DMA_MINALIGN   SMP_CACHE_BYTES
0053
0054 /*
0055  * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
0056  * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
0057  * alignment for any atomic64_t embedded in buffer.
0058  * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
0059  * value of 4 (and not 8) in ARC ABI.
0060  */
0061 #if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
0062 #define ARCH_SLAB_MINALIGN  8
0063 #endif
0064
0065 extern int ioc_enable;
0066 extern unsigned long perip_base, perip_end;
0067
0068 #endif  /* !__ASSEMBLY__ */
0069
0070 /* Instruction cache related Auxiliary registers */
0071 #define ARC_REG_IC_BCR      0x77    /* Build Config reg */
0072 #define ARC_REG_IC_IVIC     0x10
0073 #define ARC_REG_IC_CTRL     0x11
0074 #define ARC_REG_IC_IVIR     0x16
0075 #define ARC_REG_IC_ENDR     0x17
0076 #define ARC_REG_IC_IVIL     0x19
0077 #define ARC_REG_IC_PTAG     0x1E
0078 #define ARC_REG_IC_PTAG_HI  0x1F
0079
0080 /* Bit val in IC_CTRL */
0081 #define IC_CTRL_DIS     0x1
0082
0083 /* Data cache related Auxiliary registers */
0084 #define ARC_REG_DC_BCR      0x72    /* Build Config reg */
0085 #define ARC_REG_DC_IVDC     0x47
0086 #define ARC_REG_DC_CTRL     0x48
0087 #define ARC_REG_DC_IVDL     0x4A
0088 #define ARC_REG_DC_FLSH     0x4B
0089 #define ARC_REG_DC_FLDL     0x4C
0090 #define ARC_REG_DC_STARTR   0x4D
0091 #define ARC_REG_DC_ENDR     0x4E
0092 #define ARC_REG_DC_PTAG     0x5C
0093 #define ARC_REG_DC_PTAG_HI  0x5F
0094
0095 /* Bit val in DC_CTRL */
0096 #define DC_CTRL_DIS     0x001
0097 #define DC_CTRL_INV_MODE_FLUSH  0x040
0098 #define DC_CTRL_FLUSH_STATUS    0x100
0099 #define DC_CTRL_RGN_OP_INV  0x200
0100 #define DC_CTRL_RGN_OP_MSK  0x200
0101
0102 /*System-level cache (L2 cache) related Auxiliary registers */
0103 #define ARC_REG_SLC_CFG     0x901
0104 #define ARC_REG_SLC_CTRL    0x903
0105 #define ARC_REG_SLC_FLUSH   0x904
0106 #define ARC_REG_SLC_INVALIDATE  0x905
0107 #define ARC_AUX_SLC_IVDL    0x910
0108 #define ARC_AUX_SLC_FLDL    0x912
0109 #define ARC_REG_SLC_RGN_START   0x914
0110 #define ARC_REG_SLC_RGN_START1  0x915
0111 #define ARC_REG_SLC_RGN_END 0x916
0112 #define ARC_REG_SLC_RGN_END1    0x917
0113
0114 /* Bit val in SLC_CONTROL */
0115 #define SLC_CTRL_DIS        0x001
0116 #define SLC_CTRL_IM     0x040
0117 #define SLC_CTRL_BUSY       0x100
0118 #define SLC_CTRL_RGN_OP_INV 0x200
0119
0120 /* IO coherency related Auxiliary registers */
0121 #define ARC_REG_IO_COH_ENABLE   0x500
0122 #define ARC_IO_COH_ENABLE_BIT   BIT(0)
0123 #define ARC_REG_IO_COH_PARTIAL  0x501
0124 #define ARC_IO_COH_PARTIAL_BIT  BIT(0)
0125 #define ARC_REG_IO_COH_AP0_BASE 0x508
0126 #define ARC_REG_IO_COH_AP0_SIZE 0x509
0127
0128 #endif /* _ASM_CACHE_H */