include/asm/arcregs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0004  */
0005
0006 #ifndef _ASM_ARC_ARCREGS_H
0007 #define _ASM_ARC_ARCREGS_H
0008
0009 /* Build Configuration Registers */
0010 #define ARC_REG_AUX_DCCM    0x18    /* DCCM Base Addr ARCv2 */
0011 #define ARC_REG_ERP_CTRL    0x3F    /* ARCv2 Error protection control */
0012 #define ARC_REG_DCCM_BASE_BUILD 0x61    /* DCCM Base Addr ARCompact */
0013 #define ARC_REG_CRC_BCR     0x62
0014 #define ARC_REG_VECBASE_BCR 0x68
0015 #define ARC_REG_PERIBASE_BCR    0x69
0016 #define ARC_REG_FP_BCR      0x6B    /* ARCompact: Single-Precision FPU */
0017 #define ARC_REG_DPFP_BCR    0x6C    /* ARCompact: Dbl Precision FPU */
0018 #define ARC_REG_ERP_BUILD   0xc7    /* ARCv2 Error protection Build: ECC/Parity */
0019 #define ARC_REG_FP_V2_BCR   0xc8    /* ARCv2 FPU */
0020 #define ARC_REG_SLC_BCR     0xce
0021 #define ARC_REG_DCCM_BUILD  0x74    /* DCCM size (common) */
0022 #define ARC_REG_AP_BCR      0x76
0023 #define ARC_REG_ICCM_BUILD  0x78    /* ICCM size (common) */
0024 #define ARC_REG_XY_MEM_BCR  0x79
0025 #define ARC_REG_MAC_BCR     0x7a
0026 #define ARC_REG_MUL_BCR     0x7b
0027 #define ARC_REG_SWAP_BCR    0x7c
0028 #define ARC_REG_NORM_BCR    0x7d
0029 #define ARC_REG_MIXMAX_BCR  0x7e
0030 #define ARC_REG_BARREL_BCR  0x7f
0031 #define ARC_REG_D_UNCACH_BCR    0x6A
0032 #define ARC_REG_BPU_BCR     0xc0
0033 #define ARC_REG_ISA_CFG_BCR 0xc1
0034 #define ARC_REG_LPB_BUILD   0xE9    /* ARCv2 Loop Buffer Build */
0035 #define ARC_REG_RTT_BCR     0xF2
0036 #define ARC_REG_IRQ_BCR     0xF3
0037 #define ARC_REG_MICRO_ARCH_BCR  0xF9    /* ARCv2 Product revision */
0038 #define ARC_REG_SMART_BCR   0xFF
0039 #define ARC_REG_CLUSTER_BCR 0xcf
0040 #define ARC_REG_AUX_ICCM    0x208   /* ICCM Base Addr (ARCv2) */
0041 #define ARC_REG_LPB_CTRL    0x488   /* ARCv2 Loop Buffer control */
0042 #define ARC_REG_FPU_CTRL    0x300
0043 #define ARC_REG_FPU_STATUS  0x301
0044
0045 /* Common for ARCompact and ARCv2 status register */
0046 #define ARC_REG_STATUS32    0x0A
0047
0048 /* status32 Bits Positions */
0049 #define STATUS_AE_BIT       5   /* Exception active */
0050 #define STATUS_DE_BIT       6   /* PC is in delay slot */
0051 #define STATUS_U_BIT        7   /* User/Kernel mode */
0052 #define STATUS_Z_BIT            11
0053 #define STATUS_L_BIT        12  /* Loop inhibit */
0054
0055 /* These masks correspond to the status word(STATUS_32) bits */
0056 #define STATUS_AE_MASK      (1<<STATUS_AE_BIT)
0057 #define STATUS_DE_MASK      (1<<STATUS_DE_BIT)
0058 #define STATUS_U_MASK       (1<<STATUS_U_BIT)
0059 #define STATUS_Z_MASK       (1<<STATUS_Z_BIT)
0060 #define STATUS_L_MASK       (1<<STATUS_L_BIT)
0061
0062 /*
0063  * ECR: Exception Cause Reg bits-n-pieces
0064  * [23:16] = Exception Vector
0065  * [15: 8] = Exception Cause Code
0066  * [ 7: 0] = Exception Parameters (for certain types only)
0067  */
0068 #ifdef CONFIG_ISA_ARCOMPACT
0069 #define ECR_V_MEM_ERR           0x01
0070 #define ECR_V_INSN_ERR          0x02
0071 #define ECR_V_MACH_CHK          0x20
0072 #define ECR_V_ITLB_MISS         0x21
0073 #define ECR_V_DTLB_MISS         0x22
0074 #define ECR_V_PROTV         0x23
0075 #define ECR_V_TRAP          0x25
0076 #else
0077 #define ECR_V_MEM_ERR           0x01
0078 #define ECR_V_INSN_ERR          0x02
0079 #define ECR_V_MACH_CHK          0x03
0080 #define ECR_V_ITLB_MISS         0x04
0081 #define ECR_V_DTLB_MISS         0x05
0082 #define ECR_V_PROTV         0x06
0083 #define ECR_V_TRAP          0x09
0084 #define ECR_V_MISALIGN          0x0d
0085 #endif
0086
0087 /* DTLB Miss and Protection Violation Cause Codes */
0088
0089 #define ECR_C_PROTV_INST_FETCH      0x00
0090 #define ECR_C_PROTV_LOAD        0x01
0091 #define ECR_C_PROTV_STORE       0x02
0092 #define ECR_C_PROTV_XCHG        0x03
0093 #define ECR_C_PROTV_MISALIG_DATA    0x04
0094
0095 #define ECR_C_BIT_PROTV_MISALIG_DATA    10
0096
0097 /* Machine Check Cause Code Values */
0098 #define ECR_C_MCHK_DUP_TLB      0x01
0099
0100 /* DTLB Miss Exception Cause Code Values */
0101 #define ECR_C_BIT_DTLB_LD_MISS      8
0102 #define ECR_C_BIT_DTLB_ST_MISS      9
0103
0104 /* Auxiliary registers */
0105 #define AUX_IDENTITY        4
0106 #define AUX_EXEC_CTRL       8
0107 #define AUX_INTR_VEC_BASE   0x25
0108 #define AUX_VOL         0x5e
0109
0110 /*
0111  * Floating Pt Registers
0112  * Status regs are read-only (build-time) so need not be saved/restored
0113  */
0114 #define ARC_AUX_FP_STAT         0x300
0115 #define ARC_AUX_DPFP_1L         0x301
0116 #define ARC_AUX_DPFP_1H         0x302
0117 #define ARC_AUX_DPFP_2L         0x303
0118 #define ARC_AUX_DPFP_2H         0x304
0119 #define ARC_AUX_DPFP_STAT       0x305
0120
0121 /*
0122  * DSP-related registers
0123  * Registers names must correspond to dsp_callee_regs structure fields names
0124  * for automatic offset calculation in DSP_AUX_SAVE_RESTORE macros.
0125  */
0126 #define ARC_AUX_DSP_BUILD   0x7A
0127 #define ARC_AUX_ACC0_LO     0x580
0128 #define ARC_AUX_ACC0_GLO    0x581
0129 #define ARC_AUX_ACC0_HI     0x582
0130 #define ARC_AUX_ACC0_GHI    0x583
0131 #define ARC_AUX_DSP_BFLY0   0x598
0132 #define ARC_AUX_DSP_CTRL    0x59F
0133 #define ARC_AUX_DSP_FFT_CTRL    0x59E
0134
0135 #define ARC_AUX_AGU_BUILD   0xCC
0136 #define ARC_AUX_AGU_AP0     0x5C0
0137 #define ARC_AUX_AGU_AP1     0x5C1
0138 #define ARC_AUX_AGU_AP2     0x5C2
0139 #define ARC_AUX_AGU_AP3     0x5C3
0140 #define ARC_AUX_AGU_OS0     0x5D0
0141 #define ARC_AUX_AGU_OS1     0x5D1
0142 #define ARC_AUX_AGU_MOD0    0x5E0
0143 #define ARC_AUX_AGU_MOD1    0x5E1
0144 #define ARC_AUX_AGU_MOD2    0x5E2
0145 #define ARC_AUX_AGU_MOD3    0x5E3
0146
0147 #ifndef __ASSEMBLY__
0148
0149 #include <soc/arc/aux.h>
0150
0151 /* Helpers */
0152 #define TO_KB(bytes)        ((bytes) >> 10)
0153 #define TO_MB(bytes)        (TO_KB(bytes) >> 10)
0154 #define PAGES_TO_KB(n_pages)    ((n_pages) << (PAGE_SHIFT - 10))
0155 #define PAGES_TO_MB(n_pages)    (PAGES_TO_KB(n_pages) >> 10)
0156
0157
0158 /*
0159  ***************************************************************
0160  * Build Configuration Registers, with encoded hardware config
0161  */
0162 struct bcr_identity {
0163 #ifdef CONFIG_CPU_BIG_ENDIAN
0164     unsigned int chip_id:16, cpu_id:8, family:8;
0165 #else
0166     unsigned int family:8, cpu_id:8, chip_id:16;
0167 #endif
0168 };
0169
0170 struct bcr_isa_arcv2 {
0171 #ifdef CONFIG_CPU_BIG_ENDIAN
0172     unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
0173              pad1:12, ver:8;
0174 #else
0175     unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
0176              ldd:1, pad2:4, div_rem:4;
0177 #endif
0178 };
0179
0180 struct bcr_uarch_build_arcv2 {
0181 #ifdef CONFIG_CPU_BIG_ENDIAN
0182     unsigned int pad:8, prod:8, maj:8, min:8;
0183 #else
0184     unsigned int min:8, maj:8, prod:8, pad:8;
0185 #endif
0186 };
0187
0188 struct bcr_mpy {
0189 #ifdef CONFIG_CPU_BIG_ENDIAN
0190     unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
0191 #else
0192     unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
0193 #endif
0194 };
0195
0196 struct bcr_iccm_arcompact {
0197 #ifdef CONFIG_CPU_BIG_ENDIAN
0198     unsigned int base:16, pad:5, sz:3, ver:8;
0199 #else
0200     unsigned int ver:8, sz:3, pad:5, base:16;
0201 #endif
0202 };
0203
0204 struct bcr_iccm_arcv2 {
0205 #ifdef CONFIG_CPU_BIG_ENDIAN
0206     unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
0207 #else
0208     unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
0209 #endif
0210 };
0211
0212 struct bcr_dccm_arcompact {
0213 #ifdef CONFIG_CPU_BIG_ENDIAN
0214     unsigned int res:21, sz:3, ver:8;
0215 #else
0216     unsigned int ver:8, sz:3, res:21;
0217 #endif
0218 };
0219
0220 struct bcr_dccm_arcv2 {
0221 #ifdef CONFIG_CPU_BIG_ENDIAN
0222     unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
0223 #else
0224     unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
0225 #endif
0226 };
0227
0228 /* ARCompact: Both SP and DP FPU BCRs have same format */
0229 struct bcr_fp_arcompact {
0230 #ifdef CONFIG_CPU_BIG_ENDIAN
0231     unsigned int fast:1, ver:8;
0232 #else
0233     unsigned int ver:8, fast:1;
0234 #endif
0235 };
0236
0237 struct bcr_fp_arcv2 {
0238 #ifdef CONFIG_CPU_BIG_ENDIAN
0239     unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
0240 #else
0241     unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
0242 #endif
0243 };
0244
0245 struct bcr_actionpoint {
0246 #ifdef CONFIG_CPU_BIG_ENDIAN
0247     unsigned int pad:21, min:1, num:2, ver:8;
0248 #else
0249     unsigned int ver:8, num:2, min:1, pad:21;
0250 #endif
0251 };
0252
0253 #include <soc/arc/timers.h>
0254
0255 struct bcr_bpu_arcompact {
0256 #ifdef CONFIG_CPU_BIG_ENDIAN
0257     unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
0258 #else
0259     unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
0260 #endif
0261 };
0262
0263 struct bcr_bpu_arcv2 {
0264 #ifdef CONFIG_CPU_BIG_ENDIAN
0265     unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
0266 #else
0267     unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
0268 #endif
0269 };
0270
0271 /* Error Protection Build: ECC/Parity */
0272 struct bcr_erp {
0273 #ifdef CONFIG_CPU_BIG_ENDIAN
0274     unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
0275 #else
0276     unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
0277 #endif
0278 };
0279
0280 /* Error Protection Control */
0281 struct ctl_erp {
0282 #ifdef CONFIG_CPU_BIG_ENDIAN
0283     unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
0284 #else
0285     unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
0286 #endif
0287 };
0288
0289 struct bcr_lpb {
0290 #ifdef CONFIG_CPU_BIG_ENDIAN
0291     unsigned int pad:16, entries:8, ver:8;
0292 #else
0293     unsigned int ver:8, entries:8, pad:16;
0294 #endif
0295 };
0296
0297 struct bcr_generic {
0298 #ifdef CONFIG_CPU_BIG_ENDIAN
0299     unsigned int info:24, ver:8;
0300 #else
0301     unsigned int ver:8, info:24;
0302 #endif
0303 };
0304
0305 /*
0306  *******************************************************************
0307  * Generic structures to hold build configuration used at runtime
0308  */
0309
0310 struct cpuinfo_arc_mmu {
0311     unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
0312     unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
0313 };
0314
0315 struct cpuinfo_arc_cache {
0316     unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
0317 };
0318
0319 struct cpuinfo_arc_bpu {
0320     unsigned int ver, full, num_cache, num_pred, ret_stk;
0321 };
0322
0323 struct cpuinfo_arc_ccm {
0324     unsigned int base_addr, sz;
0325 };
0326
0327 struct cpuinfo_arc {
0328     struct cpuinfo_arc_cache icache, dcache, slc;
0329     struct cpuinfo_arc_mmu mmu;
0330     struct cpuinfo_arc_bpu bpu;
0331     struct bcr_identity core;
0332     struct bcr_isa_arcv2 isa;
0333     const char *release, *name;
0334     unsigned int vec_base;
0335     struct cpuinfo_arc_ccm iccm, dccm;
0336     struct {
0337         unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
0338                  fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
0339                  ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,
0340                  timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
0341     } extn;
0342     struct bcr_mpy extn_mpy;
0343 };
0344
0345 extern struct cpuinfo_arc cpuinfo_arc700[];
0346
0347 static inline int is_isa_arcv2(void)
0348 {
0349     return IS_ENABLED(CONFIG_ISA_ARCV2);
0350 }
0351
0352 static inline int is_isa_arcompact(void)
0353 {
0354     return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
0355 }
0356
0357 #endif /* __ASEMBLY__ */
0358
0359 #endif /* _ASM_ARC_ARCREGS_H */