0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
0004 */
0005
0006 /*
0007 * Device tree for AXC001 770D/EM6/AS221 CPU card
0008 * Note that this file only supports the 770D CPU
0009 */
0010
0011 /include/ "skeleton.dtsi"
0012
0013 / {
0014 compatible = "snps,arc";
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 cpu_card {
0019 compatible = "simple-bus";
0020 #address-cells = <1>;
0021 #size-cells = <1>;
0022
0023 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
0024
0025 core_clk: core_clk {
0026 #clock-cells = <0>;
0027 compatible = "fixed-clock";
0028 clock-frequency = <750000000>;
0029 };
0030
0031 input_clk: input-clk {
0032 #clock-cells = <0>;
0033 compatible = "fixed-clock";
0034 clock-frequency = <33333333>;
0035 };
0036
0037 core_intc: arc700-intc@cpu {
0038 compatible = "snps,arc700-intc";
0039 interrupt-controller;
0040 #interrupt-cells = <1>;
0041 };
0042
0043 /*
0044 * this GPIO block ORs all interrupts on CPU card (creg,..)
0045 * to uplink only 1 IRQ to ARC core intc
0046 */
0047 dw-apb-gpio@2000 {
0048 compatible = "snps,dw-apb-gpio";
0049 reg = < 0x2000 0x80 >;
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 ictl_intc: gpio-controller@0 {
0054 compatible = "snps,dw-apb-gpio-port";
0055 gpio-controller;
0056 #gpio-cells = <2>;
0057 snps,nr-gpios = <30>;
0058 reg = <0>;
0059 interrupt-controller;
0060 #interrupt-cells = <2>;
0061 interrupt-parent = <&core_intc>;
0062 interrupts = <15>;
0063 };
0064 };
0065
0066 debug_uart: dw-apb-uart@5000 {
0067 compatible = "snps,dw-apb-uart";
0068 reg = <0x5000 0x100>;
0069 clock-frequency = <33333000>;
0070 interrupt-parent = <&ictl_intc>;
0071 interrupts = <19 4>;
0072 baud = <115200>;
0073 reg-shift = <2>;
0074 reg-io-width = <4>;
0075 };
0076
0077 arcpct0: pct {
0078 compatible = "snps,arc700-pct";
0079 };
0080 };
0081
0082 /*
0083 * This INTC is actually connected to DW APB GPIO
0084 * which acts as a wire between MB INTC and CPU INTC.
0085 * GPIO INTC is configured in platform init code
0086 * and here we mimic direct connection from MB INTC to
0087 * CPU INTC, thus we set "interrupts = <7>" instead of
0088 * "interrupts = <12>"
0089 *
0090 * This intc actually resides on MB, but we move it here to
0091 * avoid duplicating the MB dtsi file given that IRQ from
0092 * this intc to cpu intc are different for axs101 and axs103
0093 */
0094 mb_intc: interrupt-controller@e0012000 {
0095 #interrupt-cells = <1>;
0096 compatible = "snps,dw-apb-ictl";
0097 reg = < 0x0 0xe0012000 0x0 0x200 >;
0098 interrupt-controller;
0099 interrupt-parent = <&core_intc>;
0100 interrupts = < 7 >;
0101 };
0102
0103 memory {
0104 device_type = "memory";
0105 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
0106 reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
0107 };
0108
0109 reserved-memory {
0110 #address-cells = <2>;
0111 #size-cells = <2>;
0112 ranges;
0113 /*
0114 * We just move frame buffer area to the very end of
0115 * available DDR. And even though in case of ARC770 there's
0116 * no strict requirement for a frame-buffer to be in any
0117 * particular location it allows us to use the same
0118 * base board's DT node for ARC PGU as for ARc HS38.
0119 */
0120 frame_buffer: frame_buffer@9e000000 {
0121 compatible = "shared-dma-pool";
0122 reg = <0x0 0x9e000000 0x0 0x2000000>;
0123 no-map;
0124 };
0125 };
0126 };
