0001 # SPDX-License-Identifier: GPL-2.0-only
0002 #
0003 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0004 #
0005
0006 config ARC
0007 def_bool y
0008 select ARC_TIMERS
0009 select ARCH_HAS_CACHE_LINE_SIZE
0010 select ARCH_HAS_DEBUG_VM_PGTABLE
0011 select ARCH_HAS_DMA_PREP_COHERENT
0012 select ARCH_HAS_PTE_SPECIAL
0013 select ARCH_HAS_SETUP_DMA_OPS
0014 select ARCH_HAS_SYNC_DMA_FOR_CPU
0015 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
0016 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
0017 select ARCH_32BIT_OFF_T
0018 select BUILDTIME_TABLE_SORT
0019 select CLONE_BACKWARDS
0020 select COMMON_CLK
0021 select DMA_DIRECT_REMAP
0022 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
0023 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
0024 select GENERIC_IRQ_SHOW
0025 select GENERIC_PCI_IOMAP
0026 select GENERIC_PENDING_IRQ if SMP
0027 select GENERIC_SCHED_CLOCK
0028 select GENERIC_SMP_IDLE_THREAD
0029 select HAVE_ARCH_KGDB
0030 select HAVE_ARCH_TRACEHOOK
0031 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
0032 select HAVE_DEBUG_STACKOVERFLOW
0033 select HAVE_DEBUG_KMEMLEAK
0034 select HAVE_IOREMAP_PROT
0035 select HAVE_KERNEL_GZIP
0036 select HAVE_KERNEL_LZMA
0037 select HAVE_KPROBES
0038 select HAVE_KRETPROBES
0039 select HAVE_REGS_AND_STACK_ACCESS_API
0040 select HAVE_MOD_ARCH_SPECIFIC
0041 select HAVE_PERF_EVENTS
0042 select HAVE_SYSCALL_TRACEPOINTS
0043 select IRQ_DOMAIN
0044 select MODULES_USE_ELF_RELA
0045 select OF
0046 select OF_EARLY_FLATTREE
0047 select PCI_SYSCALL if PCI
0048 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
0049 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
0050 select TRACE_IRQFLAGS_SUPPORT
0051
0052 config LOCKDEP_SUPPORT
0053 def_bool y
0054
0055 config SCHED_OMIT_FRAME_POINTER
0056 def_bool y
0057
0058 config GENERIC_CSUM
0059 def_bool y
0060
0061 config ARCH_FLATMEM_ENABLE
0062 def_bool y
0063
0064 config MMU
0065 def_bool y
0066
0067 config NO_IOPORT_MAP
0068 def_bool y
0069
0070 config GENERIC_CALIBRATE_DELAY
0071 def_bool y
0072
0073 config GENERIC_HWEIGHT
0074 def_bool y
0075
0076 config STACKTRACE_SUPPORT
0077 def_bool y
0078 select STACKTRACE
0079
0080 menu "ARC Architecture Configuration"
0081
0082 menu "ARC Platform/SoC/Board"
0083
0084 source "arch/arc/plat-tb10x/Kconfig"
0085 source "arch/arc/plat-axs10x/Kconfig"
0086 source "arch/arc/plat-hsdk/Kconfig"
0087
0088 endmenu
0089
0090 choice
0091 prompt "ARC Instruction Set"
0092 default ISA_ARCV2
0093
0094 config ISA_ARCOMPACT
0095 bool "ARCompact ISA"
0096 select CPU_NO_EFFICIENT_FFS
0097 help
0098 The original ARC ISA of ARC600/700 cores
0099
0100 config ISA_ARCV2
0101 bool "ARC ISA v2"
0102 select ARC_TIMERS_64BIT
0103 help
0104 ISA for the Next Generation ARC-HS cores
0105
0106 endchoice
0107
0108 menu "ARC CPU Configuration"
0109
0110 choice
0111 prompt "ARC Core"
0112 default ARC_CPU_770 if ISA_ARCOMPACT
0113 default ARC_CPU_HS if ISA_ARCV2
0114
0115 config ARC_CPU_770
0116 bool "ARC770"
0117 depends on ISA_ARCOMPACT
0118 select ARC_HAS_SWAPE
0119 help
0120 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
0121 This core has a bunch of cool new features:
0122 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
0123 Shared Address Spaces (for sharing TLB entries in MMU)
0124 -Caches: New Prog Model, Region Flush
0125 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
0126
0127 config ARC_CPU_HS
0128 bool "ARC-HS"
0129 depends on ISA_ARCV2
0130 help
0131 Support for ARC HS38x Cores based on ARCv2 ISA
0132 The notable features are:
0133 - SMP configurations of up to 4 cores with coherency
0134 - Optional L2 Cache and IO-Coherency
0135 - Revised Interrupt Architecture (multiple priorites, reg banks,
0136 auto stack switch, auto regfile save/restore)
0137 - MMUv4 (PIPT dcache, Huge Pages)
0138 - Instructions for
0139 * 64bit load/store: LDD, STD
0140 * Hardware assisted divide/remainder: DIV, REM
0141 * Function prologue/epilogue: ENTER_S, LEAVE_S
0142 * IRQ enable/disable: CLRI, SETI
0143 * pop count: FFS, FLS
0144 * SETcc, BMSKN, XBFU...
0145
0146 endchoice
0147
0148 config ARC_TUNE_MCPU
0149 string "Override default -mcpu compiler flag"
0150 default ""
0151 help
0152 Override default -mcpu=xxx compiler flag (which is set depending on
0153 the ISA version) with the specified value.
0154 NOTE: If specified flag isn't supported by current compiler the
0155 ISA default value will be used as a fallback.
0156
0157 config CPU_BIG_ENDIAN
0158 bool "Enable Big Endian Mode"
0159 help
0160 Build kernel for Big Endian Mode of ARC CPU
0161
0162 config SMP
0163 bool "Symmetric Multi-Processing"
0164 select ARC_MCIP if ISA_ARCV2
0165 help
0166 This enables support for systems with more than one CPU.
0167
0168 if SMP
0169
0170 config NR_CPUS
0171 int "Maximum number of CPUs (2-4096)"
0172 range 2 4096
0173 default "4"
0174
0175 config ARC_SMP_HALT_ON_RESET
0176 bool "Enable Halt-on-reset boot mode"
0177 help
0178 In SMP configuration cores can be configured as Halt-on-reset
0179 or they could all start at same time. For Halt-on-reset, non
0180 masters are parked until Master kicks them so they can start off
0181 at designated entry point. For other case, all jump to common
0182 entry point and spin wait for Master's signal.
0183
0184 endif #SMP
0185
0186 config ARC_MCIP
0187 bool "ARConnect Multicore IP (MCIP) Support "
0188 depends on ISA_ARCV2
0189 default y if SMP
0190 help
0191 This IP block enables SMP in ARC-HS38 cores.
0192 It provides for cross-core interrupts, multi-core debug
0193 hardware semaphores, shared memory,....
0194
0195 menuconfig ARC_CACHE
0196 bool "Enable Cache Support"
0197 default y
0198
0199 if ARC_CACHE
0200
0201 config ARC_CACHE_LINE_SHIFT
0202 int "Cache Line Length (as power of 2)"
0203 range 5 7
0204 default "6"
0205 help
0206 Starting with ARC700 4.9, Cache line length is configurable,
0207 This option specifies "N", with Line-len = 2 power N
0208 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
0209 Linux only supports same line lengths for I and D caches.
0210
0211 config ARC_HAS_ICACHE
0212 bool "Use Instruction Cache"
0213 default y
0214
0215 config ARC_HAS_DCACHE
0216 bool "Use Data Cache"
0217 default y
0218
0219 config ARC_CACHE_PAGES
0220 bool "Per Page Cache Control"
0221 default y
0222 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
0223 help
0224 This can be used to over-ride the global I/D Cache Enable on a
0225 per-page basis (but only for pages accessed via MMU such as
0226 Kernel Virtual address or User Virtual Address)
0227 TLB entries have a per-page Cache Enable Bit.
0228 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
0229 Global DISABLE + Per Page ENABLE won't work
0230
0231 config ARC_CACHE_VIPT_ALIASING
0232 bool "Support VIPT Aliasing D$"
0233 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
0234
0235 endif #ARC_CACHE
0236
0237 config ARC_HAS_ICCM
0238 bool "Use ICCM"
0239 help
0240 Single Cycle RAMS to store Fast Path Code
0241
0242 config ARC_ICCM_SZ
0243 int "ICCM Size in KB"
0244 default "64"
0245 depends on ARC_HAS_ICCM
0246
0247 config ARC_HAS_DCCM
0248 bool "Use DCCM"
0249 help
0250 Single Cycle RAMS to store Fast Path Data
0251
0252 config ARC_DCCM_SZ
0253 int "DCCM Size in KB"
0254 default "64"
0255 depends on ARC_HAS_DCCM
0256
0257 config ARC_DCCM_BASE
0258 hex "DCCM map address"
0259 default "0xA0000000"
0260 depends on ARC_HAS_DCCM
0261
0262 choice
0263 prompt "MMU Version"
0264 default ARC_MMU_V3 if ISA_ARCOMPACT
0265 default ARC_MMU_V4 if ISA_ARCV2
0266
0267 config ARC_MMU_V3
0268 bool "MMU v3"
0269 depends on ISA_ARCOMPACT
0270 help
0271 Introduced with ARC700 4.10: New Features
0272 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
0273 Shared Address Spaces (SASID)
0274
0275 config ARC_MMU_V4
0276 bool "MMU v4"
0277 depends on ISA_ARCV2
0278
0279 endchoice
0280
0281
0282 choice
0283 prompt "MMU Page Size"
0284 default ARC_PAGE_SIZE_8K
0285
0286 config ARC_PAGE_SIZE_8K
0287 bool "8KB"
0288 help
0289 Choose between 8k vs 16k
0290
0291 config ARC_PAGE_SIZE_16K
0292 bool "16KB"
0293
0294 config ARC_PAGE_SIZE_4K
0295 bool "4KB"
0296 depends on ARC_MMU_V3 || ARC_MMU_V4
0297
0298 endchoice
0299
0300 choice
0301 prompt "MMU Super Page Size"
0302 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
0303 default ARC_HUGEPAGE_2M
0304
0305 config ARC_HUGEPAGE_2M
0306 bool "2MB"
0307
0308 config ARC_HUGEPAGE_16M
0309 bool "16MB"
0310
0311 endchoice
0312
0313 config PGTABLE_LEVELS
0314 int "Number of Page table levels"
0315 default 2
0316
0317 config ARC_COMPACT_IRQ_LEVELS
0318 depends on ISA_ARCOMPACT
0319 bool "Setup Timer IRQ as high Priority"
0320 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
0321 depends on !SMP
0322
0323 config ARC_FPU_SAVE_RESTORE
0324 bool "Enable FPU state persistence across context switch"
0325 help
0326 ARCompact FPU has internal registers to assist with Double precision
0327 Floating Point operations. There are control and stauts registers
0328 for floating point exceptions and rounding modes. These are
0329 preserved across task context switch when enabled.
0330
0331 config ARC_CANT_LLSC
0332 def_bool n
0333
0334 config ARC_HAS_LLSC
0335 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
0336 default y
0337 depends on !ARC_CANT_LLSC
0338
0339 config ARC_HAS_SWAPE
0340 bool "Insn: SWAPE (endian-swap)"
0341 default y
0342
0343 if ISA_ARCV2
0344
0345 config ARC_USE_UNALIGNED_MEM_ACCESS
0346 bool "Enable unaligned access in HW"
0347 default y
0348 select HAVE_EFFICIENT_UNALIGNED_ACCESS
0349 help
0350 The ARC HS architecture supports unaligned memory access
0351 which is disabled by default. Enable unaligned access in
0352 hardware and use software to use it
0353
0354 config ARC_HAS_LL64
0355 bool "Insn: 64bit LDD/STD"
0356 help
0357 Enable gcc to generate 64-bit load/store instructions
0358 ISA mandates even/odd registers to allow encoding of two
0359 dest operands with 2 possible source operands.
0360 default y
0361
0362 config ARC_HAS_DIV_REM
0363 bool "Insn: div, divu, rem, remu"
0364 default y
0365
0366 config ARC_HAS_ACCL_REGS
0367 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
0368 default y
0369 help
0370 Depending on the configuration, CPU can contain accumulator reg-pair
0371 (also referred to as r58:r59). These can also be used by gcc as GPR so
0372 kernel needs to save/restore per process
0373
0374 config ARC_DSP_HANDLED
0375 def_bool n
0376
0377 config ARC_DSP_SAVE_RESTORE_REGS
0378 def_bool n
0379
0380 choice
0381 prompt "DSP support"
0382 default ARC_DSP_NONE
0383 help
0384 Depending on the configuration, CPU can contain DSP registers
0385 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
0386 Below are options describing how to handle these registers in
0387 interrupt entry / exit and in context switch.
0388
0389 config ARC_DSP_NONE
0390 bool "No DSP extension presence in HW"
0391 help
0392 No DSP extension presence in HW
0393
0394 config ARC_DSP_KERNEL
0395 bool "DSP extension in HW, no support for userspace"
0396 select ARC_HAS_ACCL_REGS
0397 select ARC_DSP_HANDLED
0398 help
0399 DSP extension presence in HW, no support for DSP-enabled userspace
0400 applications. We don't save / restore DSP registers and only do
0401 some minimal preparations so userspace won't be able to break kernel
0402
0403 config ARC_DSP_USERSPACE
0404 bool "Support DSP for userspace apps"
0405 select ARC_HAS_ACCL_REGS
0406 select ARC_DSP_HANDLED
0407 select ARC_DSP_SAVE_RESTORE_REGS
0408 help
0409 DSP extension presence in HW, support save / restore DSP registers to
0410 run DSP-enabled userspace applications
0411
0412 config ARC_DSP_AGU_USERSPACE
0413 bool "Support DSP with AGU for userspace apps"
0414 select ARC_HAS_ACCL_REGS
0415 select ARC_DSP_HANDLED
0416 select ARC_DSP_SAVE_RESTORE_REGS
0417 help
0418 DSP and AGU extensions presence in HW, support save / restore DSP
0419 and AGU registers to run DSP-enabled userspace applications
0420 endchoice
0421
0422 config ARC_IRQ_NO_AUTOSAVE
0423 bool "Disable hardware autosave regfile on interrupts"
0424 default n
0425 help
0426 On HS cores, taken interrupt auto saves the regfile on stack.
0427 This is programmable and can be optionally disabled in which case
0428 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
0429
0430 config ARC_LPB_DISABLE
0431 bool "Disable loop buffer (LPB)"
0432 help
0433 On HS cores, loop buffer (LPB) is programmable in runtime and can
0434 be optionally disabled.
0435
0436 endif # ISA_ARCV2
0437
0438 endmenu # "ARC CPU Configuration"
0439
0440 config LINUX_LINK_BASE
0441 hex "Kernel link address"
0442 default "0x80000000"
0443 help
0444 ARC700 divides the 32 bit phy address space into two equal halves
0445 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
0446 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
0447 Typically Linux kernel is linked at the start of untransalted addr,
0448 hence the default value of 0x8zs.
0449 However some customers have peripherals mapped at this addr, so
0450 Linux needs to be scooted a bit.
0451 If you don't know what the above means, leave this setting alone.
0452 This needs to match memory start address specified in Device Tree
0453
0454 config LINUX_RAM_BASE
0455 hex "RAM base address"
0456 default LINUX_LINK_BASE
0457 help
0458 By default Linux is linked at base of RAM. However in some special
0459 cases (such as HSDK), Linux can't be linked at start of DDR, hence
0460 this option.
0461
0462 config HIGHMEM
0463 bool "High Memory Support"
0464 select HAVE_ARCH_PFN_VALID
0465 select KMAP_LOCAL
0466 help
0467 With ARC 2G:2G address split, only upper 2G is directly addressable by
0468 kernel. Enable this to potentially allow access to rest of 2G and PAE
0469 in future
0470
0471 config ARC_HAS_PAE40
0472 bool "Support for the 40-bit Physical Address Extension"
0473 depends on ISA_ARCV2
0474 select HIGHMEM
0475 select PHYS_ADDR_T_64BIT
0476 help
0477 Enable access to physical memory beyond 4G, only supported on
0478 ARC cores with 40 bit Physical Addressing support
0479
0480 config ARC_KVADDR_SIZE
0481 int "Kernel Virtual Address Space size (MB)"
0482 range 0 512
0483 default "256"
0484 help
0485 The kernel address space is carved out of 256MB of translated address
0486 space for catering to vmalloc, modules, pkmap, fixmap. This however may
0487 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
0488 this to be stretched to 512 MB (by extending into the reserved
0489 kernel-user gutter)
0490
0491 config ARC_CURR_IN_REG
0492 bool "Dedicate Register r25 for current_task pointer"
0493 default y
0494 help
0495 This reserved Register R25 to point to Current Task in
0496 kernel mode. This saves memory access for each such access
0497
0498
0499 config ARC_EMUL_UNALIGNED
0500 bool "Emulate unaligned memory access (userspace only)"
0501 select SYSCTL_ARCH_UNALIGN_NO_WARN
0502 select SYSCTL_ARCH_UNALIGN_ALLOW
0503 depends on ISA_ARCOMPACT
0504 help
0505 This enables misaligned 16 & 32 bit memory access from user space.
0506 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
0507 potential bugs in code
0508
0509 config HZ
0510 int "Timer Frequency"
0511 default 100
0512
0513 config ARC_METAWARE_HLINK
0514 bool "Support for Metaware debugger assisted Host access"
0515 help
0516 This options allows a Linux userland apps to directly access
0517 host file system (open/creat/read/write etc) with help from
0518 Metaware Debugger. This can come in handy for Linux-host communication
0519 when there is no real usable peripheral such as EMAC.
0520
0521 menuconfig ARC_DBG
0522 bool "ARC debugging"
0523 default y
0524
0525 if ARC_DBG
0526
0527 config ARC_DW2_UNWIND
0528 bool "Enable DWARF specific kernel stack unwind"
0529 default y
0530 select KALLSYMS
0531 help
0532 Compiles the kernel with DWARF unwind information and can be used
0533 to get stack backtraces.
0534
0535 If you say Y here the resulting kernel image will be slightly larger
0536 but not slower, and it will give very useful debugging information.
0537 If you don't debug the kernel, you can say N, but we may not be able
0538 to solve problems without frame unwind information
0539
0540 config ARC_DBG_JUMP_LABEL
0541 bool "Paranoid checks in Static Keys (jump labels) code"
0542 depends on JUMP_LABEL
0543 default y if STATIC_KEYS_SELFTEST
0544 help
0545 Enable paranoid checks and self-test of both ARC-specific and generic
0546 part of static keys (jump labels) related code.
0547 endif
0548
0549 config ARC_BUILTIN_DTB_NAME
0550 string "Built in DTB"
0551 help
0552 Set the name of the DTB to embed in the vmlinux binary
0553 Leaving it blank selects the minimal "skeleton" dtb
0554
0555 endmenu # "ARC Architecture Configuration"
0556
0557 config FORCE_MAX_ZONEORDER
0558 int "Maximum zone order"
0559 default "12" if ARC_HUGEPAGE_16M
0560 default "11"
0561
0562 source "kernel/power/Kconfig"
