alpha/kernel/pci_impl.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  linux/arch/alpha/kernel/pci_impl.h
0004  *
0005  * This file contains declarations and inline functions for interfacing
0006  * with the PCI initialization routines.
0007  */
0008
0009 struct pci_dev;
0010 struct pci_controller;
0011 struct pci_iommu_arena;
0012
0013 /*
0014  * We can't just blindly use 64K for machines with EISA busses; they
0015  * may also have PCI-PCI bridges present, and then we'd configure the
0016  * bridge incorrectly.
0017  *
0018  * Also, we start at 0x8000 or 0x9000, in hopes to get all devices'
0019  * IO space areas allocated *before* 0xC000; this is because certain
0020  * BIOSes (Millennium for one) use PCI Config space "mechanism #2"
0021  * accesses to probe the bus. If a device's registers appear at 0xC000,
0022  * it may see an INx/OUTx at that address during BIOS emulation of the
0023  * VGA BIOS, and some cards, notably Adaptec 2940UW, take mortal offense.
0024  */
0025
0026 #define EISA_DEFAULT_IO_BASE    0x9000  /* start above 8th slot */
0027 #define DEFAULT_IO_BASE     0x8000  /* start at 8th slot */
0028
0029 /*
0030  * We try to make the DEFAULT_MEM_BASE addresses *always* have more than
0031  * a single bit set. This is so that devices like the broken Myrinet card
0032  * will always have a PCI memory address that will never match a IDSEL
0033  * address in PCI Config space, which can cause problems with early rev cards.
0034  */
0035
0036 /*
0037  * An XL is AVANTI (APECS) family, *but* it has only 27 bits of ISA address
0038  * that get passed through the PCI<->ISA bridge chip. Although this causes
0039  * us to set the PCI->Mem window bases lower than normal, we still allocate
0040  * PCI bus devices' memory addresses *below* the low DMA mapping window,
0041  * and hope they fit below 64Mb (to avoid conflicts), and so that they can
0042  * be accessed via SPARSE space.
0043  *
0044  * We accept the risk that a broken Myrinet card will be put into a true XL
0045  * and thus can more easily run into the problem described below.
0046  */
0047 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
0048
0049 /*
0050  * APECS and LCA have only 34 bits for physical addresses, thus limiting PCI
0051  * bus memory addresses for SPARSE access to be less than 128Mb.
0052  */
0053 #define APECS_AND_LCA_DEFAULT_MEM_BASE ((16+2)*1024*1024)
0054
0055 /*
0056  * Because MCPCIA and T2 core logic support more bits for
0057  * physical addresses, they should allow an expanded range of SPARSE
0058  * memory addresses.  However, we do not use them all, in order to
0059  * avoid the HAE manipulation that would be needed.
0060  */
0061 #define MCPCIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
0062 #define T2_DEFAULT_MEM_BASE ((16+1)*1024*1024)
0063
0064 /*
0065  * Because CIA and PYXIS have more bits for physical addresses,
0066  * they support an expanded range of SPARSE memory addresses.
0067  */
0068 #define DEFAULT_MEM_BASE ((128+16)*1024*1024)
0069
0070 /* ??? Experimenting with no HAE for CIA.  */
0071 #define CIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
0072
0073 #define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024)
0074
0075 #define DEFAULT_AGP_APER_SIZE   (64*1024*1024)
0076
0077 /*
0078  * A small note about bridges and interrupts.  The DECchip 21050 (and
0079  * later) adheres to the PCI-PCI bridge specification.  This says that
0080  * the interrupts on the other side of a bridge are swizzled in the
0081  * following manner:
0082  *
0083  * Dev    Interrupt   Interrupt
0084  *        Pin on      Pin on
0085  *        Device      Connector
0086  *
0087  *   4    A           A
0088  *        B           B
0089  *        C           C
0090  *        D           D
0091  *
0092  *   5    A           B
0093  *        B           C
0094  *        C           D
0095  *        D           A
0096  *
0097  *   6    A           C
0098  *        B           D
0099  *        C           A
0100  *        D           B
0101  *
0102  *   7    A           D
0103  *        B           A
0104  *        C           B
0105  *        D           C
0106  *
0107  *   Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
0108  *   Thus, each swizzle is ((pin-1) + (device#-4)) % 4
0109  *
0110  *   pci_swizzle_interrupt_pin() swizzles for exactly one bridge.  The routine
0111  *   pci_common_swizzle() handles multiple bridges.  But there are a
0112  *   couple boards that do strange things.
0113  */
0114
0115
0116 /* The following macro is used to implement the table-based irq mapping
0117    function for all single-bus Alphas.  */
0118
0119 #define COMMON_TABLE_LOOKUP                     \
0120 ({ long _ctl_ = -1;                             \
0121    if (slot >= min_idsel && slot <= max_idsel && pin < irqs_per_slot)   \
0122      _ctl_ = irq_tab[slot - min_idsel][pin];                \
0123    _ctl_; })
0124
0125
0126 /* A PCI IOMMU allocation arena.  There are typically two of these
0127    regions per bus.  */
0128 /* ??? The 8400 has a 32-byte pte entry, and the entire table apparently
0129    lives directly on the host bridge (no tlb?).  We don't support this
0130    machine, but if we ever did, we'd need to parameterize all this quite
0131    a bit further.  Probably with per-bus operation tables.  */
0132
0133 struct pci_iommu_arena
0134 {
0135     spinlock_t lock;
0136     struct pci_controller *hose;
0137 #define IOMMU_INVALID_PTE 0x2 /* 32:63 bits MBZ */
0138 #define IOMMU_RESERVED_PTE 0xface
0139     unsigned long *ptes;
0140     dma_addr_t dma_base;
0141     unsigned int size;
0142     unsigned int next_entry;
0143     unsigned int align_entry;
0144 };
0145
0146 #if defined(CONFIG_ALPHA_SRM) && \
0147     (defined(CONFIG_ALPHA_CIA) || defined(CONFIG_ALPHA_LCA) || \
0148      defined(CONFIG_ALPHA_AVANTI))
0149 # define NEED_SRM_SAVE_RESTORE
0150 #else
0151 # undef NEED_SRM_SAVE_RESTORE
0152 #endif
0153
0154 #if defined(CONFIG_ALPHA_GENERIC) || defined(NEED_SRM_SAVE_RESTORE)
0155 # define ALPHA_RESTORE_SRM_SETUP
0156 #else
0157 # undef ALPHA_RESTORE_SRM_SETUP
0158 #endif
0159
0160 #ifdef ALPHA_RESTORE_SRM_SETUP
0161 extern void pci_restore_srm_config(void);
0162 #else
0163 #define pci_restore_srm_config()    do {} while (0)
0164 #endif
0165
0166 /* The hose list.  */
0167 extern struct pci_controller *hose_head, **hose_tail;
0168 extern struct pci_controller *pci_isa_hose;
0169
0170 extern unsigned long alpha_agpgart_size;
0171
0172 extern void common_init_pci(void);
0173 #define common_swizzle pci_common_swizzle
0174 extern struct pci_controller *alloc_pci_controller(void);
0175 extern struct resource *alloc_resource(void);
0176
0177 extern struct pci_iommu_arena *iommu_arena_new_node(int,
0178                             struct pci_controller *,
0179                                 dma_addr_t, unsigned long,
0180                                 unsigned long);
0181 extern struct pci_iommu_arena *iommu_arena_new(struct pci_controller *,
0182                            dma_addr_t, unsigned long,
0183                            unsigned long);
0184 extern const char *const pci_io_names[];
0185 extern const char *const pci_mem_names[];
0186 extern const char pci_hae0_name[];
0187
0188 extern unsigned long size_for_memory(unsigned long max);
0189
0190 extern int iommu_reserve(struct pci_iommu_arena *, long, long);
0191 extern int iommu_release(struct pci_iommu_arena *, long, long);
0192 extern int iommu_bind(struct pci_iommu_arena *, long, long, struct page **);
0193 extern int iommu_unbind(struct pci_iommu_arena *, long, long);
0194
0195