include/asm/wrperfmon.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Definitions for use with the Alpha wrperfmon PAL call.
0004  */
0005
0006 #ifndef __ALPHA_WRPERFMON_H
0007 #define __ALPHA_WRPERFMON_H
0008
0009 /* Following commands are implemented on all CPUs */
0010 #define PERFMON_CMD_DISABLE 0
0011 #define PERFMON_CMD_ENABLE 1
0012 #define PERFMON_CMD_DESIRED_EVENTS 2
0013 #define PERFMON_CMD_LOGGING_OPTIONS 3
0014 /* Following commands on EV5/EV56/PCA56 only */
0015 #define PERFMON_CMD_INT_FREQ 4
0016 #define PERFMON_CMD_ENABLE_CLEAR 7
0017 /* Following commands are on EV5 and better CPUs */
0018 #define PERFMON_CMD_READ 5
0019 #define PERFMON_CMD_WRITE 6
0020 /* Following command are on EV6 and better CPUs */
0021 #define PERFMON_CMD_ENABLE_WRITE 7
0022 /* Following command are on EV67 and better CPUs */
0023 #define PERFMON_CMD_I_STAT 8
0024 #define PERFMON_CMD_PMPC 9
0025
0026
0027 /* EV5/EV56/PCA56 Counters */
0028 #define EV5_PCTR_0 (1UL<<0)
0029 #define EV5_PCTR_1 (1UL<<1)
0030 #define EV5_PCTR_2 (1UL<<2)
0031
0032 #define EV5_PCTR_0_COUNT_SHIFT 48
0033 #define EV5_PCTR_1_COUNT_SHIFT 32
0034 #define EV5_PCTR_2_COUNT_SHIFT 16
0035
0036 #define EV5_PCTR_0_COUNT_MASK 0xffffUL
0037 #define EV5_PCTR_1_COUNT_MASK 0xffffUL
0038 #define EV5_PCTR_2_COUNT_MASK 0x3fffUL
0039
0040 /* EV6 Counters */
0041 #define EV6_PCTR_0 (1UL<<0)
0042 #define EV6_PCTR_1 (1UL<<1)
0043
0044 #define EV6_PCTR_0_COUNT_SHIFT 28
0045 #define EV6_PCTR_1_COUNT_SHIFT 6
0046
0047 #define EV6_PCTR_0_COUNT_MASK 0xfffffUL
0048 #define EV6_PCTR_1_COUNT_MASK 0xfffffUL
0049
0050 /* EV67 (and subsequent) counters */
0051 #define EV67_PCTR_0 (1UL<<0)
0052 #define EV67_PCTR_1 (1UL<<1)
0053
0054 #define EV67_PCTR_0_COUNT_SHIFT 28
0055 #define EV67_PCTR_1_COUNT_SHIFT 6
0056
0057 #define EV67_PCTR_0_COUNT_MASK 0xfffffUL
0058 #define EV67_PCTR_1_COUNT_MASK 0xfffffUL
0059
0060
0061 /*
0062  * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint
0063  *  in Table E-23 regarding the bits that set the event PCTR 1 counts.
0064  *  Hopefully what we have here is correct.
0065  */
0066 #define EV6_PCTR_0_EVENT_MASK 0x10UL
0067 #define EV6_PCTR_1_EVENT_MASK 0x0fUL
0068
0069 /* EV6 Events */
0070 #define EV6_PCTR_0_CYCLES (0UL << 4)
0071 #define EV6_PCTR_0_INSTRUCTIONS (1UL << 4)
0072
0073 #define EV6_PCTR_1_CYCLES 0
0074 #define EV6_PCTR_1_BRANCHES 1
0075 #define EV6_PCTR_1_BRANCH_MISPREDICTS 2
0076 #define EV6_PCTR_1_DTB_SINGLE_MISSES 3
0077 #define EV6_PCTR_1_DTB_DOUBLE_MISSES 4
0078 #define EV6_PCTR_1_ITB_MISSES 5
0079 #define EV6_PCTR_1_UNALIGNED_TRAPS 6
0080 #define EV6_PCTR_1_REPLY_TRAPS 7
0081
0082 /* From the Alpha Architecture Reference Manual, 4th edn., 2002 */
0083 #define EV67_PCTR_MODE_MASK 0x10UL
0084 #define EV67_PCTR_EVENT_MASK 0x0CUL
0085
0086 #define EV67_PCTR_MODE_PROFILEME (1UL<<4)
0087 #define EV67_PCTR_MODE_AGGREGATE (0UL<<4)
0088
0089 #define EV67_PCTR_INSTR_CYCLES (0UL<<2)
0090 #define EV67_PCTR_CYCLES_UNDEF (1UL<<2)
0091 #define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)
0092 #define EV67_PCTR_CYCLES_MBOX (3UL<<2)
0093
0094 #endif