include/asm/pgtable.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ALPHA_PGTABLE_H
0003 #define _ALPHA_PGTABLE_H
0004
0005 #include <asm-generic/pgtable-nopud.h>
0006
0007 /*
0008  * This file contains the functions and defines necessary to modify and use
0009  * the Alpha page table tree.
0010  *
0011  * This hopefully works with any standard Alpha page-size, as defined
0012  * in <asm/page.h> (currently 8192).
0013  */
0014 #include <linux/mmzone.h>
0015
0016 #include <asm/page.h>
0017 #include <asm/processor.h>  /* For TASK_SIZE */
0018 #include <asm/machvec.h>
0019 #include <asm/setup.h>
0020
0021 struct mm_struct;
0022 struct vm_area_struct;
0023
0024 /* Certain architectures need to do special things when PTEs
0025  * within a page table are directly modified.  Thus, the following
0026  * hook is made available.
0027  */
0028 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
0029 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
0030
0031 /* PMD_SHIFT determines the size of the area a second-level page table can map */
0032 #define PMD_SHIFT   (PAGE_SHIFT + (PAGE_SHIFT-3))
0033 #define PMD_SIZE    (1UL << PMD_SHIFT)
0034 #define PMD_MASK    (~(PMD_SIZE-1))
0035
0036 /* PGDIR_SHIFT determines what a third-level page table entry can map */
0037 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
0038 #define PGDIR_SIZE  (1UL << PGDIR_SHIFT)
0039 #define PGDIR_MASK  (~(PGDIR_SIZE-1))
0040
0041 /*
0042  * Entries per page directory level:  the Alpha is three-level, with
0043  * all levels having a one-page page table.
0044  */
0045 #define PTRS_PER_PTE    (1UL << (PAGE_SHIFT-3))
0046 #define PTRS_PER_PMD    (1UL << (PAGE_SHIFT-3))
0047 #define PTRS_PER_PGD    (1UL << (PAGE_SHIFT-3))
0048 #define USER_PTRS_PER_PGD   (TASK_SIZE / PGDIR_SIZE)
0049
0050 /* Number of pointers that fit on a page:  this will go away. */
0051 #define PTRS_PER_PAGE   (1UL << (PAGE_SHIFT-3))
0052
0053 #ifdef CONFIG_ALPHA_LARGE_VMALLOC
0054 #define VMALLOC_START       0xfffffe0000000000
0055 #else
0056 #define VMALLOC_START       (-2*PGDIR_SIZE)
0057 #endif
0058 #define VMALLOC_END     (-PGDIR_SIZE)
0059
0060 /*
0061  * OSF/1 PAL-code-imposed page table bits
0062  */
0063 #define _PAGE_VALID 0x0001
0064 #define _PAGE_FOR   0x0002  /* used for page protection (fault on read) */
0065 #define _PAGE_FOW   0x0004  /* used for page protection (fault on write) */
0066 #define _PAGE_FOE   0x0008  /* used for page protection (fault on exec) */
0067 #define _PAGE_ASM   0x0010
0068 #define _PAGE_KRE   0x0100  /* xxx - see below on the "accessed" bit */
0069 #define _PAGE_URE   0x0200  /* xxx */
0070 #define _PAGE_KWE   0x1000  /* used to do the dirty bit in software */
0071 #define _PAGE_UWE   0x2000  /* used to do the dirty bit in software */
0072
0073 /* .. and these are ours ... */
0074 #define _PAGE_DIRTY 0x20000
0075 #define _PAGE_ACCESSED  0x40000
0076
0077 /*
0078  * NOTE! The "accessed" bit isn't necessarily exact:  it can be kept exactly
0079  * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
0080  * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use
0081  * the KRE/URE bits to watch for it. That way we don't need to overload the
0082  * KWE/UWE bits with both handling dirty and accessed.
0083  *
0084  * Note that the kernel uses the accessed bit just to check whether to page
0085  * out a page or not, so it doesn't have to be exact anyway.
0086  */
0087
0088 #define __DIRTY_BITS    (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
0089 #define __ACCESS_BITS   (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)
0090
0091 #define _PFN_MASK   0xFFFFFFFF00000000UL
0092
0093 #define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
0094 #define _PAGE_CHG_MASK  (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)
0095
0096 /*
0097  * All the normal masks have the "page accessed" bits on, as any time they are used,
0098  * the page is accessed. They are cleared only by the page-out routines
0099  */
0100 #define PAGE_NONE   __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE)
0101 #define PAGE_SHARED __pgprot(_PAGE_VALID | __ACCESS_BITS)
0102 #define PAGE_COPY   __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
0103 #define PAGE_READONLY   __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
0104 #define PAGE_KERNEL __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE)
0105
0106 #define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x))
0107
0108 #define _PAGE_P(x) _PAGE_NORMAL((x) | (((x) & _PAGE_FOW)?0:_PAGE_FOW))
0109 #define _PAGE_S(x) _PAGE_NORMAL(x)
0110
0111 /*
0112  * The hardware can handle write-only mappings, but as the Alpha
0113  * architecture does byte-wide writes with a read-modify-write
0114  * sequence, it's not practical to have write-without-read privs.
0115  * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in
0116  * arch/alpha/mm/fault.c)
0117  */
0118     /* xwr */
0119
0120 /*
0121  * pgprot_noncached() is only for infiniband pci support, and a real
0122  * implementation for RAM would be more complicated.
0123  */
0124 #define pgprot_noncached(prot)  (prot)
0125
0126 /*
0127  * BAD_PAGETABLE is used when we need a bogus page-table, while
0128  * BAD_PAGE is used for a bogus page.
0129  *
0130  * ZERO_PAGE is a global shared page that is always zero:  used
0131  * for zero-mapped memory areas etc..
0132  */
0133 extern pte_t __bad_page(void);
0134 extern pmd_t * __bad_pagetable(void);
0135
0136 extern unsigned long __zero_page(void);
0137
0138 #define BAD_PAGETABLE   __bad_pagetable()
0139 #define BAD_PAGE    __bad_page()
0140 #define ZERO_PAGE(vaddr)    (virt_to_page(ZERO_PGE))
0141
0142 /* number of bits that fit into a memory pointer */
0143 #define BITS_PER_PTR            (8*sizeof(unsigned long))
0144
0145 /* to align the pointer to a pointer address */
0146 #define PTR_MASK            (~(sizeof(void*)-1))
0147
0148 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
0149 #define SIZEOF_PTR_LOG2         3
0150
0151 /* to find an entry in a page-table */
0152 #define PAGE_PTR(address)       \
0153   ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
0154
0155 /*
0156  * On certain platforms whose physical address space can overlap KSEG,
0157  * namely EV6 and above, we must re-twiddle the physaddr to restore the
0158  * correct high-order bits.
0159  *
0160  * This is extremely confusing until you realize that this is actually
0161  * just working around a userspace bug.  The X server was intending to
0162  * provide the physical address but instead provided the KSEG address.
0163  * Or tried to, except it's not representable.
0164  *
0165  * On Tsunami there's nothing meaningful at 0x40000000000, so this is
0166  * a safe thing to do.  Come the first core logic that does put something
0167  * in this area -- memory or whathaveyou -- then this hack will have
0168  * to go away.  So be prepared!
0169  */
0170
0171 #if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG)
0172 #error "EV6-only feature in a generic kernel"
0173 #endif
0174 #if defined(CONFIG_ALPHA_GENERIC) || \
0175     (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG))
0176 #define KSEG_PFN    (0xc0000000000UL >> PAGE_SHIFT)
0177 #define PHYS_TWIDDLE(pfn) \
0178   ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \
0179   ? ((pfn) ^= KSEG_PFN) : (pfn))
0180 #else
0181 #define PHYS_TWIDDLE(pfn) (pfn)
0182 #endif
0183
0184 /*
0185  * Conversion functions:  convert a page and protection to a page entry,
0186  * and a page entry and page directory to the page they refer to.
0187  */
0188 #define page_to_pa(page)    (page_to_pfn(page) << PAGE_SHIFT)
0189 #define pte_pfn(pte)    (pte_val(pte) >> 32)
0190
0191 #define pte_page(pte)   pfn_to_page(pte_pfn(pte))
0192 #define mk_pte(page, pgprot)                        \
0193 ({                                  \
0194     pte_t pte;                          \
0195                                     \
0196     pte_val(pte) = (page_to_pfn(page) << 32) | pgprot_val(pgprot);  \
0197     pte;                                \
0198 })
0199
0200 extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot)
0201 { pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; }
0202
0203 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
0204 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
0205
0206 extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
0207 { pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
0208
0209 extern inline void pud_set(pud_t * pudp, pmd_t * pmdp)
0210 { pud_val(*pudp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
0211
0212
0213 extern inline unsigned long
0214 pmd_page_vaddr(pmd_t pmd)
0215 {
0216     return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET;
0217 }
0218
0219 #define pmd_pfn(pmd)    (pmd_val(pmd) >> 32)
0220 #define pmd_page(pmd)   (pfn_to_page(pmd_val(pmd) >> 32))
0221 #define pud_page(pud)   (pfn_to_page(pud_val(pud) >> 32))
0222
0223 extern inline pmd_t *pud_pgtable(pud_t pgd)
0224 {
0225     return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)));
0226 }
0227
0228 extern inline int pte_none(pte_t pte)       { return !pte_val(pte); }
0229 extern inline int pte_present(pte_t pte)    { return pte_val(pte) & _PAGE_VALID; }
0230 extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
0231 {
0232     pte_val(*ptep) = 0;
0233 }
0234
0235 extern inline int pmd_none(pmd_t pmd)       { return !pmd_val(pmd); }
0236 extern inline int pmd_bad(pmd_t pmd)        { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; }
0237 extern inline int pmd_present(pmd_t pmd)    { return pmd_val(pmd) & _PAGE_VALID; }
0238 extern inline void pmd_clear(pmd_t * pmdp)  { pmd_val(*pmdp) = 0; }
0239
0240 extern inline int pud_none(pud_t pud)       { return !pud_val(pud); }
0241 extern inline int pud_bad(pud_t pud)        { return (pud_val(pud) & ~_PFN_MASK) != _PAGE_TABLE; }
0242 extern inline int pud_present(pud_t pud)    { return pud_val(pud) & _PAGE_VALID; }
0243 extern inline void pud_clear(pud_t * pudp)  { pud_val(*pudp) = 0; }
0244
0245 /*
0246  * The following only work if pte_present() is true.
0247  * Undefined behaviour if not..
0248  */
0249 extern inline int pte_write(pte_t pte)      { return !(pte_val(pte) & _PAGE_FOW); }
0250 extern inline int pte_dirty(pte_t pte)      { return pte_val(pte) & _PAGE_DIRTY; }
0251 extern inline int pte_young(pte_t pte)      { return pte_val(pte) & _PAGE_ACCESSED; }
0252
0253 extern inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) |= _PAGE_FOW; return pte; }
0254 extern inline pte_t pte_mkclean(pte_t pte)  { pte_val(pte) &= ~(__DIRTY_BITS); return pte; }
0255 extern inline pte_t pte_mkold(pte_t pte)    { pte_val(pte) &= ~(__ACCESS_BITS); return pte; }
0256 extern inline pte_t pte_mkwrite(pte_t pte)  { pte_val(pte) &= ~_PAGE_FOW; return pte; }
0257 extern inline pte_t pte_mkdirty(pte_t pte)  { pte_val(pte) |= __DIRTY_BITS; return pte; }
0258 extern inline pte_t pte_mkyoung(pte_t pte)  { pte_val(pte) |= __ACCESS_BITS; return pte; }
0259
0260 /*
0261  * The smp_rmb() in the following functions are required to order the load of
0262  * *dir (the pointer in the top level page table) with any subsequent load of
0263  * the returned pmd_t *ret (ret is data dependent on *dir).
0264  *
0265  * If this ordering is not enforced, the CPU might load an older value of
0266  * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
0267  * more details.
0268  *
0269  * Note that we never change the mm->pgd pointer after the task is running, so
0270  * pgd_offset does not require such a barrier.
0271  */
0272
0273 /* Find an entry in the second-level page table.. */
0274 extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address)
0275 {
0276     pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
0277     smp_rmb(); /* see above */
0278     return ret;
0279 }
0280 #define pmd_offset pmd_offset
0281
0282 /* Find an entry in the third-level page table.. */
0283 extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
0284 {
0285     pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
0286         + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
0287     smp_rmb(); /* see above */
0288     return ret;
0289 }
0290 #define pte_offset_kernel pte_offset_kernel
0291
0292 extern pgd_t swapper_pg_dir[1024];
0293
0294 /*
0295  * The Alpha doesn't have any external MMU info:  the kernel page
0296  * tables contain all the necessary information.
0297  */
0298 extern inline void update_mmu_cache(struct vm_area_struct * vma,
0299     unsigned long address, pte_t *ptep)
0300 {
0301 }
0302
0303 /*
0304  * Non-present pages:  high 24 bits are offset, next 8 bits type,
0305  * low 32 bits zero.
0306  */
0307 extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
0308 { pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
0309
0310 #define __swp_type(x)       (((x).val >> 32) & 0xff)
0311 #define __swp_offset(x)     ((x).val >> 40)
0312 #define __swp_entry(type, off)  ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
0313 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
0314 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
0315
0316 #define kern_addr_valid(addr)   (1)
0317
0318 #define pte_ERROR(e) \
0319     printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
0320 #define pmd_ERROR(e) \
0321     printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
0322 #define pgd_ERROR(e) \
0323     printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
0324
0325 extern void paging_init(void);
0326
0327 /* We have our own get_unmapped_area to cope with ADDR_LIMIT_32BIT.  */
0328 #define HAVE_ARCH_UNMAPPED_AREA
0329
0330 #endif /* _ALPHA_PGTABLE_H */