include/asm/mmu_context.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_MMU_CONTEXT_H
0003 #define __ALPHA_MMU_CONTEXT_H
0004
0005 /*
0006  * get a new mmu context..
0007  *
0008  * Copyright (C) 1996, Linus Torvalds
0009  */
0010
0011 #include <linux/mm_types.h>
0012 #include <linux/sched.h>
0013
0014 #include <asm/machvec.h>
0015 #include <asm/compiler.h>
0016 #include <asm-generic/mm_hooks.h>
0017
0018 /*
0019  * Force a context reload. This is needed when we change the page
0020  * table pointer or when we update the ASN of the current process.
0021  */
0022
0023 /* Don't get into trouble with dueling __EXTERN_INLINEs.  */
0024 #ifndef __EXTERN_INLINE
0025 #include <asm/io.h>
0026 #endif
0027
0028
0029 static inline unsigned long
0030 __reload_thread(struct pcb_struct *pcb)
0031 {
0032     register unsigned long a0 __asm__("$16");
0033     register unsigned long v0 __asm__("$0");
0034
0035     a0 = virt_to_phys(pcb);
0036     __asm__ __volatile__(
0037         "call_pal %2 #__reload_thread"
0038         : "=r"(v0), "=r"(a0)
0039         : "i"(PAL_swpctx), "r"(a0)
0040         : "$1", "$22", "$23", "$24", "$25");
0041
0042     return v0;
0043 }
0044
0045
0046 /*
0047  * The maximum ASN's the processor supports.  On the EV4 this is 63
0048  * but the PAL-code doesn't actually use this information.  On the
0049  * EV5 this is 127, and EV6 has 255.
0050  *
0051  * On the EV4, the ASNs are more-or-less useless anyway, as they are
0052  * only used as an icache tag, not for TB entries.  On the EV5 and EV6,
0053  * ASN's also validate the TB entries, and thus make a lot more sense.
0054  *
0055  * The EV4 ASN's don't even match the architecture manual, ugh.  And
0056  * I quote: "If a processor implements address space numbers (ASNs),
0057  * and the old PTE has the Address Space Match (ASM) bit clear (ASNs
0058  * in use) and the Valid bit set, then entries can also effectively be
0059  * made coherent by assigning a new, unused ASN to the currently
0060  * running process and not reusing the previous ASN before calling the
0061  * appropriate PALcode routine to invalidate the translation buffer (TB)".
0062  *
0063  * In short, the EV4 has a "kind of" ASN capability, but it doesn't actually
0064  * work correctly and can thus not be used (explaining the lack of PAL-code
0065  * support).
0066  */
0067 #define EV4_MAX_ASN 63
0068 #define EV5_MAX_ASN 127
0069 #define EV6_MAX_ASN 255
0070
0071 #ifdef CONFIG_ALPHA_GENERIC
0072 # define MAX_ASN    (alpha_mv.max_asn)
0073 #else
0074 # ifdef CONFIG_ALPHA_EV4
0075 #  define MAX_ASN   EV4_MAX_ASN
0076 # elif defined(CONFIG_ALPHA_EV5)
0077 #  define MAX_ASN   EV5_MAX_ASN
0078 # else
0079 #  define MAX_ASN   EV6_MAX_ASN
0080 # endif
0081 #endif
0082
0083 /*
0084  * cpu_last_asn(processor):
0085  * 63                                            0
0086  * +-------------+----------------+--------------+
0087  * | asn version | this processor | hardware asn |
0088  * +-------------+----------------+--------------+
0089  */
0090
0091 #include <asm/smp.h>
0092 #ifdef CONFIG_SMP
0093 #define cpu_last_asn(cpuid) (cpu_data[cpuid].last_asn)
0094 #else
0095 extern unsigned long last_asn;
0096 #define cpu_last_asn(cpuid) last_asn
0097 #endif /* CONFIG_SMP */
0098
0099 #define WIDTH_HARDWARE_ASN  8
0100 #define ASN_FIRST_VERSION (1UL << WIDTH_HARDWARE_ASN)
0101 #define HARDWARE_ASN_MASK ((1UL << WIDTH_HARDWARE_ASN) - 1)
0102
0103 /*
0104  * NOTE! The way this is set up, the high bits of the "asn_cache" (and
0105  * the "mm->context") are the ASN _version_ code. A version of 0 is
0106  * always considered invalid, so to invalidate another process you only
0107  * need to do "p->mm->context = 0".
0108  *
0109  * If we need more ASN's than the processor has, we invalidate the old
0110  * user TLB's (tbiap()) and start a new ASN version. That will automatically
0111  * force a new asn for any other processes the next time they want to
0112  * run.
0113  */
0114
0115 #ifndef __EXTERN_INLINE
0116 #define __EXTERN_INLINE extern inline
0117 #define __MMU_EXTERN_INLINE
0118 #endif
0119
0120 extern inline unsigned long
0121 __get_new_mm_context(struct mm_struct *mm, long cpu)
0122 {
0123     unsigned long asn = cpu_last_asn(cpu);
0124     unsigned long next = asn + 1;
0125
0126     if ((asn & HARDWARE_ASN_MASK) >= MAX_ASN) {
0127         tbiap();
0128         imb();
0129         next = (asn & ~HARDWARE_ASN_MASK) + ASN_FIRST_VERSION;
0130     }
0131     cpu_last_asn(cpu) = next;
0132     return next;
0133 }
0134
0135 __EXTERN_INLINE void
0136 ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
0137           struct task_struct *next)
0138 {
0139     /* Check if our ASN is of an older version, and thus invalid. */
0140     unsigned long asn;
0141     unsigned long mmc;
0142     long cpu = smp_processor_id();
0143
0144 #ifdef CONFIG_SMP
0145     cpu_data[cpu].asn_lock = 1;
0146     barrier();
0147 #endif
0148     asn = cpu_last_asn(cpu);
0149     mmc = next_mm->context[cpu];
0150     if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) {
0151         mmc = __get_new_mm_context(next_mm, cpu);
0152         next_mm->context[cpu] = mmc;
0153     }
0154 #ifdef CONFIG_SMP
0155     else
0156         cpu_data[cpu].need_new_asn = 1;
0157 #endif
0158
0159     /* Always update the PCB ASN.  Another thread may have allocated
0160        a new mm->context (via flush_tlb_mm) without the ASN serial
0161        number wrapping.  We have no way to detect when this is needed.  */
0162     task_thread_info(next)->pcb.asn = mmc & HARDWARE_ASN_MASK;
0163 }
0164
0165 __EXTERN_INLINE void
0166 ev4_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
0167           struct task_struct *next)
0168 {
0169     /* As described, ASN's are broken for TLB usage.  But we can
0170        optimize for switching between threads -- if the mm is
0171        unchanged from current we needn't flush.  */
0172     /* ??? May not be needed because EV4 PALcode recognizes that
0173        ASN's are broken and does a tbiap itself on swpctx, under
0174        the "Must set ASN or flush" rule.  At least this is true
0175        for a 1992 SRM, reports Joseph Martin (jmartin@hlo.dec.com).
0176        I'm going to leave this here anyway, just to Be Sure.  -- r~  */
0177     if (prev_mm != next_mm)
0178         tbiap();
0179
0180     /* Do continue to allocate ASNs, because we can still use them
0181        to avoid flushing the icache.  */
0182     ev5_switch_mm(prev_mm, next_mm, next);
0183 }
0184
0185 extern void __load_new_mm_context(struct mm_struct *);
0186
0187 #ifdef CONFIG_SMP
0188 #define check_mmu_context()                 \
0189 do {                                \
0190     int cpu = smp_processor_id();               \
0191     cpu_data[cpu].asn_lock = 0;             \
0192     barrier();                      \
0193     if (cpu_data[cpu].need_new_asn) {           \
0194         struct mm_struct * mm = current->active_mm; \
0195         cpu_data[cpu].need_new_asn = 0;         \
0196         if (!mm->context[cpu])          \
0197             __load_new_mm_context(mm);      \
0198     }                           \
0199 } while(0)
0200 #else
0201 #define check_mmu_context()  do { } while(0)
0202 #endif
0203
0204 __EXTERN_INLINE void
0205 ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
0206 {
0207     __load_new_mm_context(next_mm);
0208 }
0209
0210 __EXTERN_INLINE void
0211 ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
0212 {
0213     __load_new_mm_context(next_mm);
0214     tbiap();
0215 }
0216
0217 #ifdef CONFIG_ALPHA_GENERIC
0218 # define switch_mm(a,b,c)   alpha_mv.mv_switch_mm((a),(b),(c))
0219 # define activate_mm(x,y)   alpha_mv.mv_activate_mm((x),(y))
0220 #else
0221 # ifdef CONFIG_ALPHA_EV4
0222 #  define switch_mm(a,b,c)  ev4_switch_mm((a),(b),(c))
0223 #  define activate_mm(x,y)  ev4_activate_mm((x),(y))
0224 # else
0225 #  define switch_mm(a,b,c)  ev5_switch_mm((a),(b),(c))
0226 #  define activate_mm(x,y)  ev5_activate_mm((x),(y))
0227 # endif
0228 #endif
0229
0230 #define init_new_context init_new_context
0231 static inline int
0232 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
0233 {
0234     int i;
0235
0236     for_each_online_cpu(i)
0237         mm->context[i] = 0;
0238     if (tsk != current)
0239         task_thread_info(tsk)->pcb.ptbr
0240           = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
0241     return 0;
0242 }
0243
0244 #define enter_lazy_tlb enter_lazy_tlb
0245 static inline void
0246 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
0247 {
0248     task_thread_info(tsk)->pcb.ptbr
0249       = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
0250 }
0251
0252 #include <asm-generic/mmu_context.h>
0253
0254 #ifdef __MMU_EXTERN_INLINE
0255 #undef __EXTERN_INLINE
0256 #undef __MMU_EXTERN_INLINE
0257 #endif
0258
0259 #endif /* __ALPHA_MMU_CONTEXT_H */