include/asm/mce.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_MCE_H
0003 #define __ALPHA_MCE_H
0004
0005 /*
0006  * This is the logout header that should be common to all platforms
0007  * (assuming they are running OSF/1 PALcode, I guess).
0008  */
0009 struct el_common {
0010     unsigned int    size;       /* size in bytes of logout area */
0011     unsigned int    sbz1    : 30;   /* should be zero */
0012     unsigned int    err2    :  1;   /* second error */
0013     unsigned int    retry   :  1;   /* retry flag */
0014     unsigned int    proc_offset;    /* processor-specific offset */
0015     unsigned int    sys_offset; /* system-specific offset */
0016     unsigned int    code;       /* machine check code */
0017     unsigned int    frame_rev;  /* frame revision */
0018 };
0019
0020 /* Machine Check Frame for uncorrectable errors (Large format)
0021  *      --- This is used to log uncorrectable errors such as
0022  *          double bit ECC errors.
0023  *      --- These errors are detected by both processor and systems.
0024  */
0025 struct el_common_EV5_uncorrectable_mcheck {
0026         unsigned long   shadow[8];        /* Shadow reg. 8-14, 25           */
0027         unsigned long   paltemp[24];      /* PAL TEMP REGS.                 */
0028         unsigned long   exc_addr;         /* Address of excepting instruction*/
0029         unsigned long   exc_sum;          /* Summary of arithmetic traps.   */
0030         unsigned long   exc_mask;         /* Exception mask (from exc_sum). */
0031         unsigned long   pal_base;         /* Base address for PALcode.      */
0032         unsigned long   isr;              /* Interrupt Status Reg.          */
0033         unsigned long   icsr;             /* CURRENT SETUP OF EV5 IBOX      */
0034         unsigned long   ic_perr_stat;     /* I-CACHE Reg. <11> set Data parity
0035                                                          <12> set TAG parity*/
0036         unsigned long   dc_perr_stat;     /* D-CACHE error Reg. Bits set to 1:
0037                                                      <2> Data error in bank 0
0038                                                      <3> Data error in bank 1
0039                                                      <4> Tag error in bank 0
0040                                                      <5> Tag error in bank 1 */
0041         unsigned long   va;               /* Effective VA of fault or miss. */
0042         unsigned long   mm_stat;          /* Holds the reason for D-stream
0043                                              fault or D-cache parity errors */
0044         unsigned long   sc_addr;          /* Address that was being accessed
0045                                              when EV5 detected Secondary cache
0046                                              failure.                 */
0047         unsigned long   sc_stat;          /* Helps determine if the error was
0048                                              TAG/Data parity(Secondary Cache)*/
0049         unsigned long   bc_tag_addr;      /* Contents of EV5 BC_TAG_ADDR    */
0050         unsigned long   ei_addr;          /* Physical address of any transfer
0051                                              that is logged in EV5 EI_STAT */
0052         unsigned long   fill_syndrome;    /* For correcting ECC errors.     */
0053         unsigned long   ei_stat;          /* Helps identify reason of any
0054                                              processor uncorrectable error
0055                                              at its external interface.     */
0056         unsigned long   ld_lock;          /* Contents of EV5 LD_LOCK register*/
0057 };
0058
0059 struct el_common_EV6_mcheck {
0060     unsigned int FrameSize;     /* Bytes, including this field */
0061     unsigned int FrameFlags;    /* <31> = Retry, <30> = Second Error */
0062     unsigned int CpuOffset;     /* Offset to CPU-specific info */
0063     unsigned int SystemOffset;  /* Offset to system-specific info */
0064     unsigned int MCHK_Code;
0065     unsigned int MCHK_Frame_Rev;
0066     unsigned long I_STAT;       /* EV6 Internal Processor Registers */
0067     unsigned long DC_STAT;      /* (See the 21264 Spec) */
0068     unsigned long C_ADDR;
0069     unsigned long DC1_SYNDROME;
0070     unsigned long DC0_SYNDROME;
0071     unsigned long C_STAT;
0072     unsigned long C_STS;
0073     unsigned long MM_STAT;
0074     unsigned long EXC_ADDR;
0075     unsigned long IER_CM;
0076     unsigned long ISUM;
0077     unsigned long RESERVED0;
0078     unsigned long PAL_BASE;
0079     unsigned long I_CTL;
0080     unsigned long PCTX;
0081 };
0082
0083
0084 #endif /* __ALPHA_MCE_H */