include/asm/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * include/asm-alpha/dma.h
0004  *
0005  * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
0006  * use ISA-compatible dma.  The only extension is support for high-page
0007  * registers that allow to set the top 8 bits of a 32-bit DMA address.
0008  * This register should be written last when setting up a DMA address
0009  * as this will also enable DMA across 64 KB boundaries.
0010  */
0011
0012 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
0013  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
0014  * Written by Hennus Bergman, 1992.
0015  * High DMA channel support & info by Hannu Savolainen
0016  * and John Boyd, Nov. 1992.
0017  */
0018
0019 #ifndef _ASM_DMA_H
0020 #define _ASM_DMA_H
0021
0022 #include <linux/spinlock.h>
0023 #include <asm/io.h>
0024
0025 #define dma_outb    outb
0026 #define dma_inb     inb
0027
0028 /*
0029  * NOTES about DMA transfers:
0030  *
0031  *  controller 1: channels 0-3, byte operations, ports 00-1F
0032  *  controller 2: channels 4-7, word operations, ports C0-DF
0033  *
0034  *  - ALL registers are 8 bits only, regardless of transfer size
0035  *  - channel 4 is not used - cascades 1 into 2.
0036  *  - channels 0-3 are byte - addresses/counts are for physical bytes
0037  *  - channels 5-7 are word - addresses/counts are for physical words
0038  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
0039  *  - transfer count loaded to registers is 1 less than actual count
0040  *  - controller 2 offsets are all even (2x offsets for controller 1)
0041  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
0042  *  - page registers for 0-3 use bit 0, represent 64K pages
0043  *
0044  * DMA transfers are limited to the lower 16MB of _physical_ memory.
0045  * Note that addresses loaded into registers must be _physical_ addresses,
0046  * not logical addresses (which may differ if paging is active).
0047  *
0048  *  Address mapping for channels 0-3:
0049  *
0050  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
0051  *    |  ...  |   |  ... |   |  ... |
0052  *    |  ...  |   |  ... |   |  ... |
0053  *    |  ...  |   |  ... |   |  ... |
0054  *   P7  ...  P0  A7 ... A0  A7 ... A0
0055  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
0056  *
0057  *  Address mapping for channels 5-7:
0058  *
0059  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
0060  *    |  ...  |   \   \   ... \  \  \  ... \  \
0061  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
0062  *    |  ...  |     \   \   ... \  \  \  ... \
0063  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
0064  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
0065  *
0066  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
0067  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
0068  * the hardware level, so odd-byte transfers aren't possible).
0069  *
0070  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
0071  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
0072  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
0073  *
0074  */
0075
0076 #define MAX_DMA_CHANNELS    8
0077
0078 /*
0079   ISA DMA limitations on Alpha platforms,
0080
0081   These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
0082   just a wiring limit.
0083 */
0084
0085 /* The maximum address for ISA DMA transfer on Alpha XL, due to an
0086    hardware SIO limitation, is 64MB.
0087 */
0088 #define ALPHA_XL_MAX_ISA_DMA_ADDRESS        0x04000000UL
0089
0090 /* The maximum address for ISA DMA transfer on RUFFIAN,
0091    due to an hardware SIO limitation, is 16MB.
0092 */
0093 #define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS   0x01000000UL
0094
0095 /* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
0096    due to an hardware SIO chip limitation, is 2GB.
0097 */
0098 #define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS     0x80000000UL
0099 #define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS     0x80000000UL
0100
0101 /*
0102   Maximum address for all the others is the complete 32-bit bus
0103   address space.
0104 */
0105 #define ALPHA_MAX_ISA_DMA_ADDRESS       0x100000000UL
0106
0107 #ifdef CONFIG_ALPHA_GENERIC
0108 # define MAX_ISA_DMA_ADDRESS        (alpha_mv.max_isa_dma_address)
0109 #else
0110 # if defined(CONFIG_ALPHA_XL)
0111 #  define MAX_ISA_DMA_ADDRESS       ALPHA_XL_MAX_ISA_DMA_ADDRESS
0112 # elif defined(CONFIG_ALPHA_RUFFIAN)
0113 #  define MAX_ISA_DMA_ADDRESS       ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS
0114 # elif defined(CONFIG_ALPHA_SABLE)
0115 #  define MAX_ISA_DMA_ADDRESS       ALPHA_SABLE_MAX_ISA_DMA_ADDRESS
0116 # elif defined(CONFIG_ALPHA_ALCOR)
0117 #  define MAX_ISA_DMA_ADDRESS       ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS
0118 # else
0119 #  define MAX_ISA_DMA_ADDRESS       ALPHA_MAX_ISA_DMA_ADDRESS
0120 # endif
0121 #endif
0122
0123 /* If we have the iommu, we don't have any address limitations on DMA.
0124    Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone
0125    like i386. */
0126 #define MAX_DMA_ADDRESS     (alpha_mv.mv_pci_tbi ?  \
0127                  ~0UL : IDENT_ADDR + 0x01000000)
0128
0129 /* 8237 DMA controllers */
0130 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
0131 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
0132
0133 /* DMA controller registers */
0134 #define DMA1_CMD_REG        0x08    /* command register (w) */
0135 #define DMA1_STAT_REG       0x08    /* status register (r) */
0136 #define DMA1_REQ_REG            0x09    /* request register (w) */
0137 #define DMA1_MASK_REG       0x0A    /* single-channel mask (w) */
0138 #define DMA1_MODE_REG       0x0B    /* mode register (w) */
0139 #define DMA1_CLEAR_FF_REG   0x0C    /* clear pointer flip-flop (w) */
0140 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
0141 #define DMA1_RESET_REG      0x0D    /* Master Clear (w) */
0142 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
0143 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
0144 #define DMA1_EXT_MODE_REG   (0x400 | DMA1_MODE_REG)
0145
0146 #define DMA2_CMD_REG        0xD0    /* command register (w) */
0147 #define DMA2_STAT_REG       0xD0    /* status register (r) */
0148 #define DMA2_REQ_REG            0xD2    /* request register (w) */
0149 #define DMA2_MASK_REG       0xD4    /* single-channel mask (w) */
0150 #define DMA2_MODE_REG       0xD6    /* mode register (w) */
0151 #define DMA2_CLEAR_FF_REG   0xD8    /* clear pointer flip-flop (w) */
0152 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
0153 #define DMA2_RESET_REG      0xDA    /* Master Clear (w) */
0154 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
0155 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
0156 #define DMA2_EXT_MODE_REG   (0x400 | DMA2_MODE_REG)
0157
0158 #define DMA_ADDR_0              0x00    /* DMA address registers */
0159 #define DMA_ADDR_1              0x02
0160 #define DMA_ADDR_2              0x04
0161 #define DMA_ADDR_3              0x06
0162 #define DMA_ADDR_4              0xC0
0163 #define DMA_ADDR_5              0xC4
0164 #define DMA_ADDR_6              0xC8
0165 #define DMA_ADDR_7              0xCC
0166
0167 #define DMA_CNT_0               0x01    /* DMA count registers */
0168 #define DMA_CNT_1               0x03
0169 #define DMA_CNT_2               0x05
0170 #define DMA_CNT_3               0x07
0171 #define DMA_CNT_4               0xC2
0172 #define DMA_CNT_5               0xC6
0173 #define DMA_CNT_6               0xCA
0174 #define DMA_CNT_7               0xCE
0175
0176 #define DMA_PAGE_0              0x87    /* DMA page registers */
0177 #define DMA_PAGE_1              0x83
0178 #define DMA_PAGE_2              0x81
0179 #define DMA_PAGE_3              0x82
0180 #define DMA_PAGE_5              0x8B
0181 #define DMA_PAGE_6              0x89
0182 #define DMA_PAGE_7              0x8A
0183
0184 #define DMA_HIPAGE_0        (0x400 | DMA_PAGE_0)
0185 #define DMA_HIPAGE_1        (0x400 | DMA_PAGE_1)
0186 #define DMA_HIPAGE_2        (0x400 | DMA_PAGE_2)
0187 #define DMA_HIPAGE_3        (0x400 | DMA_PAGE_3)
0188 #define DMA_HIPAGE_4        (0x400 | DMA_PAGE_4)
0189 #define DMA_HIPAGE_5        (0x400 | DMA_PAGE_5)
0190 #define DMA_HIPAGE_6        (0x400 | DMA_PAGE_6)
0191 #define DMA_HIPAGE_7        (0x400 | DMA_PAGE_7)
0192
0193 #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
0194 #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
0195 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
0196
0197 #define DMA_AUTOINIT    0x10
0198
0199 extern spinlock_t  dma_spin_lock;
0200
0201 static __inline__ unsigned long claim_dma_lock(void)
0202 {
0203     unsigned long flags;
0204     spin_lock_irqsave(&dma_spin_lock, flags);
0205     return flags;
0206 }
0207
0208 static __inline__ void release_dma_lock(unsigned long flags)
0209 {
0210     spin_unlock_irqrestore(&dma_spin_lock, flags);
0211 }
0212
0213 /* enable/disable a specific DMA channel */
0214 static __inline__ void enable_dma(unsigned int dmanr)
0215 {
0216     if (dmanr<=3)
0217         dma_outb(dmanr,  DMA1_MASK_REG);
0218     else
0219         dma_outb(dmanr & 3,  DMA2_MASK_REG);
0220 }
0221
0222 static __inline__ void disable_dma(unsigned int dmanr)
0223 {
0224     if (dmanr<=3)
0225         dma_outb(dmanr | 4,  DMA1_MASK_REG);
0226     else
0227         dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
0228 }
0229
0230 /* Clear the 'DMA Pointer Flip Flop'.
0231  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
0232  * Use this once to initialize the FF to a known state.
0233  * After that, keep track of it. :-)
0234  * --- In order to do that, the DMA routines below should ---
0235  * --- only be used while interrupts are disabled! ---
0236  */
0237 static __inline__ void clear_dma_ff(unsigned int dmanr)
0238 {
0239     if (dmanr<=3)
0240         dma_outb(0,  DMA1_CLEAR_FF_REG);
0241     else
0242         dma_outb(0,  DMA2_CLEAR_FF_REG);
0243 }
0244
0245 /* set mode (above) for a specific DMA channel */
0246 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
0247 {
0248     if (dmanr<=3)
0249         dma_outb(mode | dmanr,  DMA1_MODE_REG);
0250     else
0251         dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
0252 }
0253
0254 /* set extended mode for a specific DMA channel */
0255 static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
0256 {
0257     if (dmanr<=3)
0258         dma_outb(ext_mode | dmanr,  DMA1_EXT_MODE_REG);
0259     else
0260         dma_outb(ext_mode | (dmanr&3),  DMA2_EXT_MODE_REG);
0261 }
0262
0263 /* Set only the page register bits of the transfer address.
0264  * This is used for successive transfers when we know the contents of
0265  * the lower 16 bits of the DMA current address register.
0266  */
0267 static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
0268 {
0269     switch(dmanr) {
0270         case 0:
0271             dma_outb(pagenr, DMA_PAGE_0);
0272             dma_outb((pagenr >> 8), DMA_HIPAGE_0);
0273             break;
0274         case 1:
0275             dma_outb(pagenr, DMA_PAGE_1);
0276             dma_outb((pagenr >> 8), DMA_HIPAGE_1);
0277             break;
0278         case 2:
0279             dma_outb(pagenr, DMA_PAGE_2);
0280             dma_outb((pagenr >> 8), DMA_HIPAGE_2);
0281             break;
0282         case 3:
0283             dma_outb(pagenr, DMA_PAGE_3);
0284             dma_outb((pagenr >> 8), DMA_HIPAGE_3);
0285             break;
0286         case 5:
0287             dma_outb(pagenr & 0xfe, DMA_PAGE_5);
0288             dma_outb((pagenr >> 8), DMA_HIPAGE_5);
0289             break;
0290         case 6:
0291             dma_outb(pagenr & 0xfe, DMA_PAGE_6);
0292             dma_outb((pagenr >> 8), DMA_HIPAGE_6);
0293             break;
0294         case 7:
0295             dma_outb(pagenr & 0xfe, DMA_PAGE_7);
0296             dma_outb((pagenr >> 8), DMA_HIPAGE_7);
0297             break;
0298     }
0299 }
0300
0301
0302 /* Set transfer address & page bits for specific DMA channel.
0303  * Assumes dma flipflop is clear.
0304  */
0305 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
0306 {
0307     if (dmanr <= 3)  {
0308         dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
0309             dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
0310     }  else  {
0311         dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
0312         dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
0313     }
0314     set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */
0315 }
0316
0317
0318 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
0319  * a specific DMA channel.
0320  * You must ensure the parameters are valid.
0321  * NOTE: from a manual: "the number of transfers is one more
0322  * than the initial word count"! This is taken into account.
0323  * Assumes dma flip-flop is clear.
0324  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
0325  */
0326 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
0327 {
0328         count--;
0329     if (dmanr <= 3)  {
0330         dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
0331         dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
0332         } else {
0333         dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
0334         dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
0335         }
0336 }
0337
0338
0339 /* Get DMA residue count. After a DMA transfer, this
0340  * should return zero. Reading this while a DMA transfer is
0341  * still in progress will return unpredictable results.
0342  * If called before the channel has been used, it may return 1.
0343  * Otherwise, it returns the number of _bytes_ left to transfer.
0344  *
0345  * Assumes DMA flip-flop is clear.
0346  */
0347 static __inline__ int get_dma_residue(unsigned int dmanr)
0348 {
0349     unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
0350                      : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
0351
0352     /* using short to get 16-bit wrap around */
0353     unsigned short count;
0354
0355     count = 1 + dma_inb(io_port);
0356     count += dma_inb(io_port) << 8;
0357
0358     return (dmanr<=3)? count : (count<<1);
0359 }
0360
0361
0362 /* These are in kernel/dma.c: */
0363 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
0364 extern void free_dma(unsigned int dmanr);   /* release it again */
0365 #define KERNEL_HAVE_CHECK_DMA
0366 extern int check_dma(unsigned int dmanr);
0367
0368 #endif /* _ASM_DMA_H */