include/asm/core_tsunami.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_TSUNAMI__H__
0003 #define __ALPHA_TSUNAMI__H__
0004
0005 #include <linux/types.h>
0006 #include <asm/compiler.h>
0007
0008 /*
0009  * TSUNAMI/TYPHOON are the internal names for the core logic chipset which
0010  * provides memory controller and PCI access for the 21264 based systems.
0011  *
0012  * This file is based on:
0013  *
0014  * Tsunami System Programmers Manual
0015  * Preliminary, Chapters 2-5
0016  *
0017  */
0018
0019 /* XXX: Do we need to conditionalize on this?  */
0020 #ifdef USE_48_BIT_KSEG
0021 #define TS_BIAS 0x80000000000UL
0022 #else
0023 #define TS_BIAS 0x10000000000UL
0024 #endif
0025
0026 /*
0027  * CChip, DChip, and PChip registers
0028  */
0029
0030 typedef struct {
0031     volatile unsigned long csr __attribute__((aligned(64)));
0032 } tsunami_64;
0033
0034 typedef struct {
0035     tsunami_64  csc;
0036     tsunami_64  mtr;
0037     tsunami_64  misc;
0038     tsunami_64  mpd;
0039     tsunami_64  aar0;
0040     tsunami_64  aar1;
0041     tsunami_64  aar2;
0042     tsunami_64  aar3;
0043     tsunami_64  dim0;
0044     tsunami_64  dim1;
0045     tsunami_64  dir0;
0046     tsunami_64  dir1;
0047     tsunami_64  drir;
0048     tsunami_64  prben;
0049     tsunami_64  iic;    /* a.k.a. iic0 */
0050     tsunami_64  wdr;    /* a.k.a. iic1 */
0051     tsunami_64  mpr0;
0052     tsunami_64  mpr1;
0053     tsunami_64  mpr2;
0054     tsunami_64  mpr3;
0055     tsunami_64  mctl;
0056     tsunami_64  __pad1;
0057     tsunami_64  ttr;
0058     tsunami_64  tdr;
0059     tsunami_64  dim2;
0060     tsunami_64  dim3;
0061     tsunami_64  dir2;
0062     tsunami_64  dir3;
0063     tsunami_64  iic2;
0064     tsunami_64  iic3;
0065 } tsunami_cchip;
0066
0067 typedef struct {
0068     tsunami_64  dsc;
0069     tsunami_64  str;
0070     tsunami_64  drev;
0071 } tsunami_dchip;
0072
0073 typedef struct {
0074     tsunami_64  wsba[4];
0075     tsunami_64  wsm[4];
0076     tsunami_64  tba[4];
0077     tsunami_64  pctl;
0078     tsunami_64  plat;
0079     tsunami_64  reserved;
0080     tsunami_64  perror;
0081     tsunami_64  perrmask;
0082     tsunami_64  perrset;
0083     tsunami_64  tlbiv;
0084     tsunami_64  tlbia;
0085     tsunami_64  pmonctl;
0086     tsunami_64  pmoncnt;
0087 } tsunami_pchip;
0088
0089 #define TSUNAMI_cchip  ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL))
0090 #define TSUNAMI_dchip  ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL))
0091 #define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL))
0092 #define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL))
0093 extern int TSUNAMI_bootcpu;
0094
0095 /*
0096  * TSUNAMI Pchip Error register.
0097  */
0098
0099 #define perror_m_lost 0x1
0100 #define perror_m_serr 0x2
0101 #define perror_m_perr 0x4
0102 #define perror_m_dcrto 0x8
0103 #define perror_m_sge 0x10
0104 #define perror_m_ape 0x20
0105 #define perror_m_ta 0x40
0106 #define perror_m_rdpe 0x80
0107 #define perror_m_nds 0x100
0108 #define perror_m_rto 0x200
0109 #define perror_m_uecc 0x400
0110 #define perror_m_cre 0x800
0111 #define perror_m_addrl 0xFFFFFFFF0000UL
0112 #define perror_m_addrh 0x7000000000000UL
0113 #define perror_m_cmd 0xF0000000000000UL
0114 #define perror_m_syn 0xFF00000000000000UL
0115 union TPchipPERROR {
0116     struct  {
0117         unsigned int perror_v_lost : 1;
0118         unsigned perror_v_serr : 1;
0119         unsigned perror_v_perr : 1;
0120         unsigned perror_v_dcrto : 1;
0121         unsigned perror_v_sge : 1;
0122         unsigned perror_v_ape : 1;
0123         unsigned perror_v_ta : 1;
0124         unsigned perror_v_rdpe : 1;
0125         unsigned perror_v_nds : 1;
0126         unsigned perror_v_rto : 1;
0127         unsigned perror_v_uecc : 1;
0128         unsigned perror_v_cre : 1;
0129         unsigned perror_v_rsvd1 : 4;
0130         unsigned perror_v_addrl : 32;
0131         unsigned perror_v_addrh : 3;
0132         unsigned perror_v_rsvd2 : 1;
0133         unsigned perror_v_cmd : 4;
0134         unsigned perror_v_syn : 8;
0135     } perror_r_bits;
0136     int perror_q_whole [2];
0137 };
0138
0139 /*
0140  * TSUNAMI Pchip Window Space Base Address register.
0141  */
0142 #define wsba_m_ena 0x1
0143 #define wsba_m_sg 0x2
0144 #define wsba_m_ptp 0x4
0145 #define wsba_m_addr 0xFFF00000
0146 #define wmask_k_sz1gb 0x3FF00000
0147 union TPchipWSBA {
0148     struct  {
0149         unsigned wsba_v_ena : 1;
0150         unsigned wsba_v_sg : 1;
0151         unsigned wsba_v_ptp : 1;
0152         unsigned wsba_v_rsvd1 : 17;
0153         unsigned wsba_v_addr : 12;
0154         unsigned wsba_v_rsvd2 : 32;
0155     } wsba_r_bits;
0156     int wsba_q_whole [2];
0157 };
0158
0159 /*
0160  * TSUNAMI Pchip Control Register
0161  */
0162 #define pctl_m_fdsc 0x1
0163 #define pctl_m_fbtb 0x2
0164 #define pctl_m_thdis 0x4
0165 #define pctl_m_chaindis 0x8
0166 #define pctl_m_tgtlat 0x10
0167 #define pctl_m_hole 0x20
0168 #define pctl_m_mwin 0x40
0169 #define pctl_m_arbena 0x80
0170 #define pctl_m_prigrp 0x7F00
0171 #define pctl_m_ppri 0x8000
0172 #define pctl_m_rsvd1 0x30000
0173 #define pctl_m_eccen 0x40000
0174 #define pctl_m_padm 0x80000
0175 #define pctl_m_cdqmax 0xF00000
0176 #define pctl_m_rev 0xFF000000
0177 #define pctl_m_crqmax 0xF00000000UL
0178 #define pctl_m_ptpmax 0xF000000000UL
0179 #define pctl_m_pclkx 0x30000000000UL
0180 #define pctl_m_fdsdis 0x40000000000UL
0181 #define pctl_m_fdwdis 0x80000000000UL
0182 #define pctl_m_ptevrfy 0x100000000000UL
0183 #define pctl_m_rpp 0x200000000000UL
0184 #define pctl_m_pid 0xC00000000000UL
0185 #define pctl_m_rsvd2 0xFFFF000000000000UL
0186
0187 union TPchipPCTL {
0188     struct {
0189         unsigned pctl_v_fdsc : 1;
0190         unsigned pctl_v_fbtb : 1;
0191         unsigned pctl_v_thdis : 1;
0192         unsigned pctl_v_chaindis : 1;
0193         unsigned pctl_v_tgtlat : 1;
0194         unsigned pctl_v_hole : 1;
0195         unsigned pctl_v_mwin : 1;
0196         unsigned pctl_v_arbena : 1;
0197         unsigned pctl_v_prigrp : 7;
0198         unsigned pctl_v_ppri : 1;
0199         unsigned pctl_v_rsvd1 : 2;
0200         unsigned pctl_v_eccen : 1;
0201         unsigned pctl_v_padm : 1;
0202         unsigned pctl_v_cdqmax : 4;
0203         unsigned pctl_v_rev : 8;
0204         unsigned pctl_v_crqmax : 4;
0205         unsigned pctl_v_ptpmax : 4;
0206         unsigned pctl_v_pclkx : 2;
0207         unsigned pctl_v_fdsdis : 1;
0208         unsigned pctl_v_fdwdis : 1;
0209         unsigned pctl_v_ptevrfy : 1;
0210         unsigned pctl_v_rpp : 1;
0211         unsigned pctl_v_pid : 2;
0212         unsigned pctl_v_rsvd2 : 16;
0213     } pctl_r_bits;
0214     int pctl_q_whole [2];
0215 };
0216
0217 /*
0218  * TSUNAMI Pchip Error Mask Register.
0219  */
0220 #define perrmask_m_lost 0x1
0221 #define perrmask_m_serr 0x2
0222 #define perrmask_m_perr 0x4
0223 #define perrmask_m_dcrto 0x8
0224 #define perrmask_m_sge 0x10
0225 #define perrmask_m_ape 0x20
0226 #define perrmask_m_ta 0x40
0227 #define perrmask_m_rdpe 0x80
0228 #define perrmask_m_nds 0x100
0229 #define perrmask_m_rto 0x200
0230 #define perrmask_m_uecc 0x400
0231 #define perrmask_m_cre 0x800
0232 #define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL
0233 union TPchipPERRMASK {
0234     struct  {
0235         unsigned int perrmask_v_lost : 1;
0236         unsigned perrmask_v_serr : 1;
0237         unsigned perrmask_v_perr : 1;
0238         unsigned perrmask_v_dcrto : 1;
0239         unsigned perrmask_v_sge : 1;
0240         unsigned perrmask_v_ape : 1;
0241         unsigned perrmask_v_ta : 1;
0242         unsigned perrmask_v_rdpe : 1;
0243         unsigned perrmask_v_nds : 1;
0244         unsigned perrmask_v_rto : 1;
0245         unsigned perrmask_v_uecc : 1;
0246         unsigned perrmask_v_cre : 1;
0247         unsigned perrmask_v_rsvd1 : 20;
0248         unsigned perrmask_v_rsvd2 : 32;
0249     } perrmask_r_bits;
0250     int perrmask_q_whole [2];
0251 };
0252
0253 /*
0254  * Memory spaces:
0255  */
0256 #define TSUNAMI_HOSE(h)     (((unsigned long)(h)) << 33)
0257 #define TSUNAMI_BASE        (IDENT_ADDR + TS_BIAS)
0258
0259 #define TSUNAMI_MEM(h)      (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL)
0260 #define _TSUNAMI_IACK_SC(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL)
0261 #define TSUNAMI_IO(h)       (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL)
0262 #define TSUNAMI_CONF(h)     (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL)
0263
0264 #define TSUNAMI_IACK_SC     _TSUNAMI_IACK_SC(0) /* hack! */
0265
0266
0267 /*
0268  * The canonical non-remaped I/O and MEM addresses have these values
0269  * subtracted out.  This is arranged so that folks manipulating ISA
0270  * devices can use their familiar numbers and have them map to bus 0.
0271  */
0272
0273 #define TSUNAMI_IO_BIAS          TSUNAMI_IO(0)
0274 #define TSUNAMI_MEM_BIAS         TSUNAMI_MEM(0)
0275
0276 /* The IO address space is larger than 0xffff */
0277 #define TSUNAMI_IO_SPACE    (TSUNAMI_CONF(0) - TSUNAMI_IO(0))
0278
0279 /* Offset between ram physical addresses and pci64 DAC bus addresses.  */
0280 #define TSUNAMI_DAC_OFFSET  (1UL << 40)
0281
0282 /*
0283  * Data structure for handling TSUNAMI machine checks:
0284  */
0285 struct el_TSUNAMI_sysdata_mcheck {
0286 };
0287
0288
0289 #ifdef __KERNEL__
0290
0291 #ifndef __EXTERN_INLINE
0292 #define __EXTERN_INLINE extern inline
0293 #define __IO_EXTERN_INLINE
0294 #endif
0295
0296 /*
0297  * I/O functions:
0298  *
0299  * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264)
0300  * can only use linear accesses to get at PCI memory and I/O spaces.
0301  */
0302
0303 /*
0304  * Memory functions.  all accesses are done through linear space.
0305  */
0306 extern void __iomem *tsunami_ioportmap(unsigned long addr);
0307 extern void __iomem *tsunami_ioremap(unsigned long addr, unsigned long size);
0308 __EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr)
0309 {
0310     return addr >= TSUNAMI_BASE;
0311 }
0312
0313 __EXTERN_INLINE int tsunami_is_mmio(const volatile void __iomem *xaddr)
0314 {
0315     unsigned long addr = (unsigned long) xaddr;
0316     return (addr & 0x100000000UL) == 0;
0317 }
0318
0319 #undef __IO_PREFIX
0320 #define __IO_PREFIX     tsunami
0321 #define tsunami_trivial_rw_bw   1
0322 #define tsunami_trivial_rw_lq   1
0323 #define tsunami_trivial_io_bw   1
0324 #define tsunami_trivial_io_lq   1
0325 #define tsunami_trivial_iounmap 1
0326 #include <asm/io_trivial.h>
0327
0328 #ifdef __IO_EXTERN_INLINE
0329 #undef __EXTERN_INLINE
0330 #undef __IO_EXTERN_INLINE
0331 #endif
0332
0333 #endif /* __KERNEL__ */
0334
0335 #endif /* __ALPHA_TSUNAMI__H__ */