include/asm/core_titan.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_TITAN__H__
0003 #define __ALPHA_TITAN__H__
0004
0005 #include <linux/types.h>
0006 #include <asm/compiler.h>
0007
0008 /*
0009  * TITAN is the internal names for a core logic chipset which provides
0010  * memory controller and PCI/AGP access for 21264 based systems.
0011  *
0012  * This file is based on:
0013  *
0014  * Titan Chipset Engineering Specification
0015  * Revision 0.12
0016  * 13 July 1999
0017  *
0018  */
0019
0020 /* XXX: Do we need to conditionalize on this?  */
0021 #ifdef USE_48_BIT_KSEG
0022 #define TI_BIAS 0x80000000000UL
0023 #else
0024 #define TI_BIAS 0x10000000000UL
0025 #endif
0026
0027 /*
0028  * CChip, DChip, and PChip registers
0029  */
0030
0031 typedef struct {
0032     volatile unsigned long csr __attribute__((aligned(64)));
0033 } titan_64;
0034
0035 typedef struct {
0036     titan_64    csc;
0037     titan_64    mtr;
0038     titan_64    misc;
0039     titan_64    mpd;
0040     titan_64    aar0;
0041     titan_64    aar1;
0042     titan_64    aar2;
0043     titan_64    aar3;
0044     titan_64    dim0;
0045     titan_64    dim1;
0046     titan_64    dir0;
0047     titan_64    dir1;
0048     titan_64    drir;
0049     titan_64    prben;
0050     titan_64    iic0;
0051     titan_64    iic1;
0052     titan_64    mpr0;
0053     titan_64    mpr1;
0054     titan_64    mpr2;
0055     titan_64    mpr3;
0056     titan_64    rsvd[2];
0057     titan_64    ttr;
0058     titan_64    tdr;
0059     titan_64    dim2;
0060     titan_64    dim3;
0061     titan_64    dir2;
0062     titan_64    dir3;
0063     titan_64    iic2;
0064     titan_64    iic3;
0065     titan_64    pwr;
0066     titan_64    reserved[17];
0067     titan_64    cmonctla;
0068     titan_64    cmonctlb;
0069     titan_64    cmoncnt01;
0070     titan_64    cmoncnt23;
0071     titan_64    cpen;
0072 } titan_cchip;
0073
0074 typedef struct {
0075     titan_64    dsc;
0076     titan_64    str;
0077     titan_64    drev;
0078     titan_64    dsc2;
0079 } titan_dchip;
0080
0081 typedef struct {
0082     titan_64    wsba[4];
0083     titan_64    wsm[4];
0084     titan_64    tba[4];
0085     titan_64    pctl;
0086     titan_64    plat;
0087     titan_64    reserved0[2];
0088     union {
0089         struct {
0090             titan_64    serror;
0091             titan_64    serren;
0092             titan_64    serrset;
0093             titan_64    reserved0;
0094             titan_64    gperror;
0095             titan_64    gperren;
0096             titan_64    gperrset;
0097             titan_64    reserved1;
0098             titan_64    gtlbiv;
0099             titan_64    gtlbia;
0100             titan_64    reserved2[2];
0101             titan_64    sctl;
0102             titan_64    reserved3[3];
0103         } g;
0104         struct {
0105             titan_64    agperror;
0106             titan_64    agperren;
0107             titan_64    agperrset;
0108             titan_64    agplastwr;
0109             titan_64    aperror;
0110             titan_64    aperren;
0111             titan_64    aperrset;
0112             titan_64    reserved0;
0113             titan_64    atlbiv;
0114             titan_64    atlbia;
0115             titan_64    reserved1[6];
0116         } a;
0117     } port_specific;
0118     titan_64    sprst;
0119     titan_64    reserved1[31];
0120 } titan_pachip_port;
0121
0122 typedef struct {
0123     titan_pachip_port   g_port;
0124     titan_pachip_port   a_port;
0125 } titan_pachip;
0126
0127 #define TITAN_cchip ((titan_cchip  *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL))
0128 #define TITAN_dchip     ((titan_dchip  *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL))
0129 #define TITAN_pachip0   ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL))
0130 #define TITAN_pachip1   ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL))
0131 extern unsigned TITAN_agp;
0132 extern int TITAN_bootcpu;
0133
0134 /*
0135  * TITAN PA-chip Window Space Base Address register.
0136  * (WSBA[0-2])
0137  */
0138 #define wsba_m_ena 0x1
0139 #define wsba_m_sg 0x2
0140 #define wsba_m_addr 0xFFF00000
0141 #define wmask_k_sz1gb 0x3FF00000
0142 union TPAchipWSBA {
0143     struct  {
0144         unsigned wsba_v_ena : 1;
0145         unsigned wsba_v_sg : 1;
0146         unsigned wsba_v_rsvd1 : 18;
0147         unsigned wsba_v_addr : 12;
0148         unsigned wsba_v_rsvd2 : 32;
0149         } wsba_r_bits;
0150     int wsba_q_whole [2];
0151 };
0152
0153 /*
0154  * TITAN PA-chip Control Register
0155  * This definition covers both the G-Port GPCTL and the A-PORT APCTL.
0156  * Bits <51:0> are the same in both cases. APCTL<63:52> are only
0157  * applicable to AGP.
0158  */
0159 #define pctl_m_fbtb             0x00000001
0160 #define pctl_m_thdis            0x00000002
0161 #define pctl_m_chaindis         0x00000004
0162 #define pctl_m_tgtlat           0x00000018
0163 #define pctl_m_hole             0x00000020
0164 #define pctl_m_mwin             0x00000040
0165 #define pctl_m_arbena           0x00000080
0166 #define pctl_m_prigrp           0x0000FF00
0167 #define pctl_m_ppri             0x00010000
0168 #define pctl_m_pcispd66         0x00020000
0169 #define pctl_m_cngstlt          0x003C0000
0170 #define pctl_m_ptpdesten        0x3FC00000
0171 #define pctl_m_dpcen            0x40000000
0172 #define pctl_m_apcen        0x0000000080000000UL
0173 #define pctl_m_dcrtv        0x0000000300000000UL
0174 #define pctl_m_en_stepping  0x0000000400000000UL
0175 #define apctl_m_rsvd1       0x000FFFF800000000UL
0176 #define apctl_m_agp_rate    0x0030000000000000UL
0177 #define apctl_m_agp_sba_en  0x0040000000000000UL
0178 #define apctl_m_agp_en      0x0080000000000000UL
0179 #define apctl_m_rsvd2       0x0100000000000000UL
0180 #define apctl_m_agp_present 0x0200000000000000UL
0181 #define apctl_agp_hp_rd     0x1C00000000000000UL
0182 #define apctl_agp_lp_rd     0xE000000000000000UL
0183 #define gpctl_m_rsvd        0xFFFFFFF800000000UL
0184 union TPAchipPCTL {
0185     struct {
0186         unsigned pctl_v_fbtb : 1;       /* A/G [0]     */
0187         unsigned pctl_v_thdis : 1;      /* A/G [1]     */
0188         unsigned pctl_v_chaindis : 1;       /* A/G [2]     */
0189         unsigned pctl_v_tgtlat : 2;     /* A/G [4:3]   */
0190         unsigned pctl_v_hole : 1;       /* A/G [5]     */
0191         unsigned pctl_v_mwin : 1;       /* A/G [6]     */
0192         unsigned pctl_v_arbena : 1;     /* A/G [7]     */
0193         unsigned pctl_v_prigrp : 8;     /* A/G [15:8]  */
0194         unsigned pctl_v_ppri : 1;       /* A/G [16]    */
0195         unsigned pctl_v_pcispd66 : 1;       /* A/G [17]    */
0196         unsigned pctl_v_cngstlt : 4;        /* A/G [21:18] */
0197         unsigned pctl_v_ptpdesten : 8;      /* A/G [29:22] */
0198         unsigned pctl_v_dpcen : 1;      /* A/G [30]    */
0199         unsigned pctl_v_apcen : 1;      /* A/G [31]    */
0200         unsigned pctl_v_dcrtv : 2;      /* A/G [33:32] */
0201         unsigned pctl_v_en_stepping :1;     /* A/G [34]    */
0202         unsigned apctl_v_rsvd1 : 17;        /* A   [51:35] */
0203         unsigned apctl_v_agp_rate : 2;      /* A   [53:52] */
0204         unsigned apctl_v_agp_sba_en : 1;    /* A   [54]    */
0205         unsigned apctl_v_agp_en : 1;        /* A   [55]    */
0206         unsigned apctl_v_rsvd2 : 1;     /* A   [56]    */
0207         unsigned apctl_v_agp_present : 1;   /* A   [57]    */
0208         unsigned apctl_v_agp_hp_rd : 3;     /* A   [60:58] */
0209         unsigned apctl_v_agp_lp_rd : 3;     /* A   [63:61] */
0210     } pctl_r_bits;
0211     unsigned int pctl_l_whole [2];
0212     unsigned long pctl_q_whole;
0213 };
0214
0215 /*
0216  * SERROR / SERREN / SERRSET
0217  */
0218 union TPAchipSERR {
0219     struct {
0220         unsigned serr_v_lost_uecc : 1;      /* [0]      */
0221         unsigned serr_v_uecc : 1;       /* [1]      */
0222         unsigned serr_v_cre : 1;        /* [2]      */
0223         unsigned serr_v_nxio : 1;       /* [3]      */
0224         unsigned serr_v_lost_cre : 1;       /* [4]      */
0225         unsigned serr_v_rsvd0 : 10;     /* [14:5]   */
0226         unsigned serr_v_addr : 32;      /* [46:15]  */
0227         unsigned serr_v_rsvd1 : 5;      /* [51:47]  */
0228         unsigned serr_v_source : 2;     /* [53:52]  */
0229         unsigned serr_v_cmd : 2;        /* [55:54]  */
0230         unsigned serr_v_syn : 8;        /* [63:56]  */
0231     } serr_r_bits;
0232     unsigned int serr_l_whole[2];
0233     unsigned long serr_q_whole;
0234 };
0235
0236 /*
0237  * GPERROR / APERROR / GPERREN / APERREN / GPERRSET / APERRSET
0238  */
0239 union TPAchipPERR {
0240     struct {
0241         unsigned long perr_v_lost : 1;          /* [0]      */
0242         unsigned long perr_v_serr : 1;      /* [1]      */
0243         unsigned long perr_v_perr : 1;      /* [2]      */
0244         unsigned long perr_v_dcrto : 1;     /* [3]      */
0245         unsigned long perr_v_sge : 1;       /* [4]      */
0246         unsigned long perr_v_ape : 1;       /* [5]      */
0247         unsigned long perr_v_ta : 1;        /* [6]      */
0248         unsigned long perr_v_dpe : 1;       /* [7]      */
0249         unsigned long perr_v_nds : 1;       /* [8]      */
0250         unsigned long perr_v_iptpr : 1;     /* [9]      */
0251         unsigned long perr_v_iptpw : 1;     /* [10]     */
0252         unsigned long perr_v_rsvd0 : 3;     /* [13:11]  */
0253         unsigned long perr_v_addr : 33;     /* [46:14]  */
0254         unsigned long perr_v_dac : 1;       /* [47]     */
0255         unsigned long perr_v_mwin : 1;      /* [48]     */
0256         unsigned long perr_v_rsvd1 : 3;     /* [51:49]  */
0257         unsigned long perr_v_cmd : 4;       /* [55:52]  */
0258         unsigned long perr_v_rsvd2 : 8;     /* [63:56]  */
0259     } perr_r_bits;
0260     unsigned int perr_l_whole[2];
0261     unsigned long perr_q_whole;
0262 };
0263
0264 /*
0265  * AGPERROR / AGPERREN / AGPERRSET
0266  */
0267 union TPAchipAGPERR {
0268     struct {
0269         unsigned agperr_v_lost : 1;     /* [0]      */
0270         unsigned agperr_v_lpqfull : 1;      /* [1]      */
0271         unsigned apgerr_v_hpqfull : 1;      /* [2]      */
0272         unsigned agperr_v_rescmd : 1;       /* [3]      */
0273         unsigned agperr_v_ipte : 1;     /* [4]      */
0274         unsigned agperr_v_ptp : 1;          /* [5]      */
0275         unsigned agperr_v_nowindow : 1;     /* [6]      */
0276         unsigned agperr_v_rsvd0 : 8;        /* [14:7]   */
0277         unsigned agperr_v_addr : 32;        /* [46:15]  */
0278         unsigned agperr_v_rsvd1 : 1;        /* [47]     */
0279         unsigned agperr_v_dac : 1;      /* [48]     */
0280         unsigned agperr_v_mwin : 1;     /* [49]     */
0281         unsigned agperr_v_cmd : 3;      /* [52:50]  */
0282         unsigned agperr_v_length : 6;       /* [58:53]  */
0283         unsigned agperr_v_fence : 1;        /* [59]     */
0284         unsigned agperr_v_rsvd2 : 4;        /* [63:60]  */
0285     } agperr_r_bits;
0286     unsigned int agperr_l_whole[2];
0287     unsigned long agperr_q_whole;
0288 };
0289 /*
0290  * Memory spaces:
0291  * Hose numbers are assigned as follows:
0292  *      0 - pachip 0 / G Port
0293  *      1 - pachip 1 / G Port
0294  *      2 - pachip 0 / A Port
0295  *          3 - pachip 1 / A Port
0296  */
0297 #define TITAN_HOSE_SHIFT       (33)
0298 #define TITAN_HOSE(h)       (((unsigned long)(h)) << TITAN_HOSE_SHIFT)
0299 #define TITAN_BASE      (IDENT_ADDR + TI_BIAS)
0300 #define TITAN_MEM(h)            (TITAN_BASE+TITAN_HOSE(h)+0x000000000UL)
0301 #define _TITAN_IACK_SC(h)       (TITAN_BASE+TITAN_HOSE(h)+0x1F8000000UL)
0302 #define TITAN_IO(h)         (TITAN_BASE+TITAN_HOSE(h)+0x1FC000000UL)
0303 #define TITAN_CONF(h)           (TITAN_BASE+TITAN_HOSE(h)+0x1FE000000UL)
0304
0305 #define TITAN_HOSE_MASK     TITAN_HOSE(3)
0306 #define TITAN_IACK_SC           _TITAN_IACK_SC(0) /* hack! */
0307
0308 /*
0309  * The canonical non-remaped I/O and MEM addresses have these values
0310  * subtracted out.  This is arranged so that folks manipulating ISA
0311  * devices can use their familiar numbers and have them map to bus 0.
0312  */
0313
0314 #define TITAN_IO_BIAS       TITAN_IO(0)
0315 #define TITAN_MEM_BIAS      TITAN_MEM(0)
0316
0317 /* The IO address space is larger than 0xffff */
0318 #define TITAN_IO_SPACE      (TITAN_CONF(0) - TITAN_IO(0))
0319
0320 /* TIG Space */
0321 #define TITAN_TIG_SPACE     (TITAN_BASE + 0x100000000UL)
0322
0323 /* Offset between ram physical addresses and pci64 DAC bus addresses.  */
0324 /* ??? Just a guess.  Ought to confirm it hasn't been moved.  */
0325 #define TITAN_DAC_OFFSET    (1UL << 40)
0326
0327 /*
0328  * Data structure for handling TITAN machine checks:
0329  */
0330 #define SCB_Q_SYSERR    0x620
0331 #define SCB_Q_PROCERR   0x630
0332 #define SCB_Q_SYSMCHK   0x660
0333 #define SCB_Q_PROCMCHK  0x670
0334 #define SCB_Q_SYSEVENT  0x680   /* environmental / system management */
0335 struct el_TITAN_sysdata_mcheck {
0336     u64 summary;    /* 0x00 */
0337     u64 c_dirx; /* 0x08 */
0338     u64 c_misc; /* 0x10 */
0339     u64 p0_serror;  /* 0x18 */
0340     u64 p0_gperror; /* 0x20 */
0341     u64 p0_aperror; /* 0x28 */
0342     u64 p0_agperror;/* 0x30 */
0343     u64 p1_serror;  /* 0x38 */
0344     u64 p1_gperror; /* 0x40 */
0345     u64 p1_aperror; /* 0x48 */
0346     u64 p1_agperror;/* 0x50 */
0347 };
0348
0349 /*
0350  * System area for a privateer 680 environmental/system management mcheck
0351  */
0352 struct el_PRIVATEER_envdata_mcheck {
0353     u64 summary;    /* 0x00 */
0354     u64 c_dirx; /* 0x08 */
0355     u64 smir;   /* 0x10 */
0356     u64 cpuir;  /* 0x18 */
0357     u64 psir;   /* 0x20 */
0358     u64 fault;  /* 0x28 */
0359     u64 sys_doors;  /* 0x30 */
0360     u64 temp_warn;  /* 0x38 */
0361     u64 fan_ctrl;   /* 0x40 */
0362     u64 code;   /* 0x48 */
0363     u64 reserved;   /* 0x50 */
0364 };
0365
0366 #ifdef __KERNEL__
0367
0368 #ifndef __EXTERN_INLINE
0369 #define __EXTERN_INLINE extern inline
0370 #define __IO_EXTERN_INLINE
0371 #endif
0372
0373 /*
0374  * I/O functions:
0375  *
0376  * TITAN, a 21??? PCI/memory support chipset for the EV6 (21264)
0377  * can only use linear accesses to get at PCI/AGP memory and I/O spaces.
0378  */
0379
0380 /*
0381  * Memory functions.  all accesses are done through linear space.
0382  */
0383 extern void __iomem *titan_ioportmap(unsigned long addr);
0384 extern void __iomem *titan_ioremap(unsigned long addr, unsigned long size);
0385 extern void titan_iounmap(volatile void __iomem *addr);
0386
0387 __EXTERN_INLINE int titan_is_ioaddr(unsigned long addr)
0388 {
0389     return addr >= TITAN_BASE;
0390 }
0391
0392 extern int titan_is_mmio(const volatile void __iomem *addr);
0393
0394 #undef __IO_PREFIX
0395 #define __IO_PREFIX     titan
0396 #define titan_trivial_rw_bw 1
0397 #define titan_trivial_rw_lq 1
0398 #define titan_trivial_io_bw 1
0399 #define titan_trivial_io_lq 1
0400 #define titan_trivial_iounmap   0
0401 #include <asm/io_trivial.h>
0402
0403 #ifdef __IO_EXTERN_INLINE
0404 #undef __EXTERN_INLINE
0405 #undef __IO_EXTERN_INLINE
0406 #endif
0407
0408 #endif /* __KERNEL__ */
0409
0410 #endif /* __ALPHA_TITAN__H__ */