include/asm/core_t2.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_T2__H__
0003 #define __ALPHA_T2__H__
0004
0005 /* Fit everything into one 128MB HAE window. */
0006 #define T2_ONE_HAE_WINDOW 1
0007
0008 #include <linux/types.h>
0009 #include <linux/spinlock.h>
0010 #include <asm/compiler.h>
0011
0012 /*
0013  * T2 is the internal name for the core logic chipset which provides
0014  * memory controller and PCI access for the SABLE-based systems.
0015  *
0016  * This file is based on:
0017  *
0018  * SABLE I/O Specification
0019  * Revision/Update Information: 1.3
0020  *
0021  * jestabro@amt.tay1.dec.com Initial Version.
0022  *
0023  */
0024
0025 #define T2_MEM_R1_MASK 0x07ffffff  /* Mem sparse region 1 mask is 27 bits */
0026
0027 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
0028 /* All LYNX machines, EV4 or EV5, use the GAMMA bias also */
0029 #define _GAMMA_BIAS     0x8000000000UL
0030
0031 #if defined(CONFIG_ALPHA_GENERIC)
0032 #define GAMMA_BIAS      alpha_mv.sys.t2.gamma_bias
0033 #elif defined(CONFIG_ALPHA_GAMMA)
0034 #define GAMMA_BIAS      _GAMMA_BIAS
0035 #else
0036 #define GAMMA_BIAS      0
0037 #endif
0038
0039 /*
0040  * Memory spaces:
0041  */
0042 #define T2_CONF             (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
0043 #define T2_IO           (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
0044 #define T2_SPARSE_MEM       (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
0045 #define T2_DENSE_MEM            (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
0046
0047 #define T2_IOCSR        (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
0048 #define T2_CERR1        (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
0049 #define T2_CERR2        (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
0050 #define T2_CERR3        (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
0051 #define T2_PERR1        (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
0052 #define T2_PERR2        (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
0053 #define T2_PSCR         (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
0054 #define T2_HAE_1        (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
0055 #define T2_HAE_2        (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
0056 #define T2_HBASE        (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
0057 #define T2_WBASE1       (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
0058 #define T2_WMASK1       (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
0059 #define T2_TBASE1       (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
0060 #define T2_WBASE2       (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
0061 #define T2_WMASK2       (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
0062 #define T2_TBASE2       (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
0063 #define T2_TLBBR        (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
0064 #define T2_IVR          (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
0065 #define T2_HAE_3        (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
0066 #define T2_HAE_4        (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
0067
0068 /* The CSRs below are T3/T4 only */
0069 #define T2_WBASE3       (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
0070 #define T2_WMASK3       (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
0071 #define T2_TBASE3       (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
0072
0073 #define T2_TDR0         (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
0074 #define T2_TDR1         (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
0075 #define T2_TDR2         (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
0076 #define T2_TDR3         (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
0077 #define T2_TDR4         (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
0078 #define T2_TDR5         (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
0079 #define T2_TDR6         (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
0080 #define T2_TDR7         (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
0081
0082 #define T2_WBASE4       (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
0083 #define T2_WMASK4       (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
0084 #define T2_TBASE4       (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
0085
0086 #define T2_AIR          (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
0087 #define T2_VAR          (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
0088 #define T2_DIR          (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
0089 #define T2_ICE          (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
0090
0091 #ifndef T2_ONE_HAE_WINDOW
0092 #define T2_HAE_ADDRESS      T2_HAE_1
0093 #endif
0094
0095 /*  T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
0096  3.8fff.ffff
0097  *
0098  *  +--------------+ 3 8000 0000
0099  *  | CPU 0 CSRs   |
0100  *  +--------------+ 3 8100 0000
0101  *  | CPU 1 CSRs   |
0102  *  +--------------+ 3 8200 0000
0103  *  | CPU 2 CSRs   |
0104  *  +--------------+ 3 8300 0000
0105  *  | CPU 3 CSRs   |
0106  *  +--------------+ 3 8400 0000
0107  *  | CPU Reserved |
0108  *  +--------------+ 3 8700 0000
0109  *  | Mem Reserved |
0110  *  +--------------+ 3 8800 0000
0111  *  | Mem 0 CSRs   |
0112  *  +--------------+ 3 8900 0000
0113  *  | Mem 1 CSRs   |
0114  *  +--------------+ 3 8a00 0000
0115  *  | Mem 2 CSRs   |
0116  *  +--------------+ 3 8b00 0000
0117  *  | Mem 3 CSRs   |
0118  *  +--------------+ 3 8c00 0000
0119  *  | Mem Reserved |
0120  *  +--------------+ 3 8e00 0000
0121  *  | PCI Bridge   |
0122  *  +--------------+ 3 8f00 0000
0123  *  | Expansion IO |
0124  *  +--------------+ 3 9000 0000
0125  *
0126  *
0127  */
0128 #define T2_CPU0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
0129 #define T2_CPU1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
0130 #define T2_CPU2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
0131 #define T2_CPU3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
0132
0133 #define T2_CPUn_BASE(n)     (T2_CPU0_BASE + (((n)&3) * 0x001000000L))
0134
0135 #define T2_MEM0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
0136 #define T2_MEM1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
0137 #define T2_MEM2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
0138 #define T2_MEM3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
0139
0140
0141 /*
0142  * Sable CPU Module CSRS
0143  *
0144  * These are CSRs for hardware other than the CPU chip on the CPU module.
0145  * The CPU module has Backup Cache control logic, Cbus control logic, and
0146  * interrupt control logic on it.  There is a duplicate tag store to speed
0147  * up maintaining cache coherency.
0148  */
0149
0150 struct sable_cpu_csr {
0151   unsigned long bcc;     long fill_00[3]; /* Backup Cache Control */
0152   unsigned long bcce;    long fill_01[3]; /* Backup Cache Correctable Error */
0153   unsigned long bccea;   long fill_02[3]; /* B-Cache Corr Err Address Latch */
0154   unsigned long bcue;    long fill_03[3]; /* B-Cache Uncorrectable Error */
0155   unsigned long bcuea;   long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */
0156   unsigned long dter;    long fill_05[3]; /* Duplicate Tag Error */
0157   unsigned long cbctl;   long fill_06[3]; /* CBus Control */
0158   unsigned long cbe;     long fill_07[3]; /* CBus Error */
0159   unsigned long cbeal;   long fill_08[3]; /* CBus Error Addr Latch low */
0160   unsigned long cbeah;   long fill_09[3]; /* CBus Error Addr Latch high */
0161   unsigned long pmbx;    long fill_10[3]; /* Processor Mailbox */
0162   unsigned long ipir;    long fill_11[3]; /* Inter-Processor Int Request */
0163   unsigned long sic;     long fill_12[3]; /* System Interrupt Clear */
0164   unsigned long adlk;    long fill_13[3]; /* Address Lock (LDxL/STxC) */
0165   unsigned long madrl;   long fill_14[3]; /* CBus Miss Address */
0166   unsigned long rev;     long fill_15[3]; /* CMIC Revision */
0167 };
0168
0169 /*
0170  * Data structure for handling T2 machine checks:
0171  */
0172 struct el_t2_frame_header {
0173     unsigned int    elcf_fid;   /* Frame ID (from above) */
0174     unsigned int    elcf_size;  /* Size of frame in bytes */
0175 };
0176
0177 struct el_t2_procdata_mcheck {
0178     unsigned long   elfmc_paltemp[32];  /* PAL TEMP REGS. */
0179     /* EV4-specific fields */
0180     unsigned long   elfmc_exc_addr; /* Addr of excepting insn. */
0181     unsigned long   elfmc_exc_sum;  /* Summary of arith traps. */
0182     unsigned long   elfmc_exc_mask; /* Exception mask (from exc_sum). */
0183     unsigned long   elfmc_iccsr;    /* IBox hardware enables. */
0184     unsigned long   elfmc_pal_base; /* Base address for PALcode. */
0185     unsigned long   elfmc_hier; /* Hardware Interrupt Enable. */
0186     unsigned long   elfmc_hirr; /* Hardware Interrupt Request. */
0187     unsigned long   elfmc_mm_csr;   /* D-stream fault info. */
0188     unsigned long   elfmc_dc_stat;  /* D-cache status (ECC/Parity Err). */
0189     unsigned long   elfmc_dc_addr;  /* EV3 Phys Addr for ECC/DPERR. */
0190     unsigned long   elfmc_abox_ctl; /* ABox Control Register. */
0191     unsigned long   elfmc_biu_stat; /* BIU Status. */
0192     unsigned long   elfmc_biu_addr; /* BUI Address. */
0193     unsigned long   elfmc_biu_ctl;  /* BIU Control. */
0194     unsigned long   elfmc_fill_syndrome; /* For correcting ECC errors. */
0195     unsigned long   elfmc_fill_addr;/* Cache block which was being read. */
0196     unsigned long   elfmc_va;   /* Effective VA of fault or miss. */
0197     unsigned long   elfmc_bc_tag;   /* Backup Cache Tag Probe Results. */
0198 };
0199
0200 /*
0201  * Sable processor specific Machine Check Data segment.
0202  */
0203
0204 struct el_t2_logout_header {
0205     unsigned int    elfl_size;  /* size in bytes of logout area. */
0206     unsigned int    elfl_sbz1:31;   /* Should be zero. */
0207     unsigned int    elfl_retry:1;   /* Retry flag. */
0208     unsigned int    elfl_procoffset; /* Processor-specific offset. */
0209     unsigned int    elfl_sysoffset;  /* Offset of system-specific. */
0210     unsigned int    elfl_error_type;    /* PAL error type code. */
0211     unsigned int    elfl_frame_rev;     /* PAL Frame revision. */
0212 };
0213 struct el_t2_sysdata_mcheck {
0214     unsigned long    elcmc_bcc;       /* CSR 0 */
0215     unsigned long    elcmc_bcce;          /* CSR 1 */
0216     unsigned long    elcmc_bccea;      /* CSR 2 */
0217     unsigned long    elcmc_bcue;          /* CSR 3 */
0218     unsigned long    elcmc_bcuea;      /* CSR 4 */
0219     unsigned long    elcmc_dter;          /* CSR 5 */
0220     unsigned long    elcmc_cbctl;      /* CSR 6 */
0221     unsigned long    elcmc_cbe;       /* CSR 7 */
0222     unsigned long    elcmc_cbeal;      /* CSR 8 */
0223     unsigned long    elcmc_cbeah;      /* CSR 9 */
0224     unsigned long    elcmc_pmbx;          /* CSR 10 */
0225     unsigned long    elcmc_ipir;          /* CSR 11 */
0226     unsigned long    elcmc_sic;       /* CSR 12 */
0227     unsigned long    elcmc_adlk;          /* CSR 13 */
0228     unsigned long    elcmc_madrl;      /* CSR 14 */
0229     unsigned long    elcmc_crrev4;     /* CSR 15 */
0230 };
0231
0232 /*
0233  * Sable memory error frame - sable pfms section 3.42
0234  */
0235 struct el_t2_data_memory {
0236     struct  el_t2_frame_header elcm_hdr;    /* ID$MEM-FERR = 0x08 */
0237     unsigned int  elcm_module;  /* Module id. */
0238     unsigned int  elcm_res04;   /* Reserved. */
0239     unsigned long elcm_merr;    /* CSR0: Error Reg 1. */
0240     unsigned long elcm_mcmd1;   /* CSR1: Command Trap 1. */
0241     unsigned long elcm_mcmd2;   /* CSR2: Command Trap 2. */
0242     unsigned long elcm_mconf;   /* CSR3: Configuration. */
0243     unsigned long elcm_medc1;   /* CSR4: EDC Status 1. */
0244     unsigned long elcm_medc2;   /* CSR5: EDC Status 2. */
0245     unsigned long elcm_medcc;   /* CSR6: EDC Control. */
0246     unsigned long elcm_msctl;   /* CSR7: Stream Buffer Control. */
0247     unsigned long elcm_mref;    /* CSR8: Refresh Control. */
0248     unsigned long elcm_filter;  /* CSR9: CRD Filter Control. */
0249 };
0250
0251
0252 /*
0253  * Sable other CPU error frame - sable pfms section 3.43
0254  */
0255 struct el_t2_data_other_cpu {
0256     short         elco_cpuid;   /* CPU ID */
0257     short         elco_res02[3];
0258     unsigned long elco_bcc; /* CSR 0 */
0259     unsigned long elco_bcce;    /* CSR 1 */
0260     unsigned long elco_bccea;   /* CSR 2 */
0261     unsigned long elco_bcue;    /* CSR 3 */
0262     unsigned long elco_bcuea;   /* CSR 4 */
0263     unsigned long elco_dter;    /* CSR 5 */
0264     unsigned long elco_cbctl;   /* CSR 6 */
0265     unsigned long elco_cbe; /* CSR 7 */
0266     unsigned long elco_cbeal;   /* CSR 8 */
0267     unsigned long elco_cbeah;   /* CSR 9 */
0268     unsigned long elco_pmbx;    /* CSR 10 */
0269     unsigned long elco_ipir;    /* CSR 11 */
0270     unsigned long elco_sic; /* CSR 12 */
0271     unsigned long elco_adlk;    /* CSR 13 */
0272     unsigned long elco_madrl;   /* CSR 14 */
0273     unsigned long elco_crrev4;  /* CSR 15 */
0274 };
0275
0276 /*
0277  * Sable other CPU error frame - sable pfms section 3.44
0278  */
0279 struct el_t2_data_t2{
0280     struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */
0281     unsigned long elct_iocsr;   /* IO Control and Status Register */
0282     unsigned long elct_cerr1;   /* Cbus Error Register 1 */
0283     unsigned long elct_cerr2;   /* Cbus Error Register 2 */
0284     unsigned long elct_cerr3;   /* Cbus Error Register 3 */
0285     unsigned long elct_perr1;   /* PCI Error Register 1 */
0286     unsigned long elct_perr2;   /* PCI Error Register 2 */
0287     unsigned long elct_hae0_1;  /* High Address Extension Register 1 */
0288     unsigned long elct_hae0_2;  /* High Address Extension Register 2 */
0289     unsigned long elct_hbase;   /* High Base Register */
0290     unsigned long elct_wbase1;  /* Window Base Register 1 */
0291     unsigned long elct_wmask1;  /* Window Mask Register 1 */
0292     unsigned long elct_tbase1;  /* Translated Base Register 1 */
0293     unsigned long elct_wbase2;  /* Window Base Register 2 */
0294     unsigned long elct_wmask2;  /* Window Mask Register 2 */
0295     unsigned long elct_tbase2;  /* Translated Base Register 2 */
0296     unsigned long elct_tdr0;    /* TLB Data Register 0 */
0297     unsigned long elct_tdr1;    /* TLB Data Register 1 */
0298     unsigned long elct_tdr2;    /* TLB Data Register 2 */
0299     unsigned long elct_tdr3;    /* TLB Data Register 3 */
0300     unsigned long elct_tdr4;    /* TLB Data Register 4 */
0301     unsigned long elct_tdr5;    /* TLB Data Register 5 */
0302     unsigned long elct_tdr6;    /* TLB Data Register 6 */
0303     unsigned long elct_tdr7;    /* TLB Data Register 7 */
0304 };
0305
0306 /*
0307  * Sable error log data structure - sable pfms section 3.40
0308  */
0309 struct el_t2_data_corrected {
0310     unsigned long elcpb_biu_stat;
0311     unsigned long elcpb_biu_addr;
0312     unsigned long elcpb_biu_ctl;
0313     unsigned long elcpb_fill_syndrome;
0314     unsigned long elcpb_fill_addr;
0315     unsigned long elcpb_bc_tag;
0316 };
0317
0318 /*
0319  * Sable error log data structure
0320  * Note there are 4 memory slots on sable (see t2.h)
0321  */
0322 struct el_t2_frame_mcheck {
0323     struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */
0324     struct el_t2_logout_header elfmc_hdr;
0325     struct el_t2_procdata_mcheck elfmc_procdata;
0326     struct el_t2_sysdata_mcheck elfmc_sysdata;
0327     struct el_t2_data_t2 elfmc_t2data;
0328     struct el_t2_data_memory elfmc_memdata[4];
0329     struct el_t2_frame_header elfmc_footer; /* empty */
0330 };
0331
0332
0333 /*
0334  * Sable error log data structures on memory errors
0335  */
0336 struct el_t2_frame_corrected {
0337     struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */
0338     struct el_t2_logout_header elfcc_hdr;
0339     struct el_t2_data_corrected elfcc_procdata;
0340 /*  struct el_t2_data_t2 elfcc_t2data;      */
0341 /*  struct el_t2_data_memory elfcc_memdata[4];  */
0342     struct el_t2_frame_header elfcc_footer; /* empty */
0343 };
0344
0345
0346 #ifdef __KERNEL__
0347
0348 #ifndef __EXTERN_INLINE
0349 #define __EXTERN_INLINE extern inline
0350 #define __IO_EXTERN_INLINE
0351 #endif
0352
0353 /*
0354  * I/O functions:
0355  *
0356  * T2 (the core logic PCI/memory support chipset for the SABLE
0357  * series of processors uses a sparse address mapping scheme to
0358  * get at PCI memory and I/O.
0359  */
0360
0361 #define vip volatile int *
0362 #define vuip    volatile unsigned int *
0363
0364 extern inline u8 t2_inb(unsigned long addr)
0365 {
0366     long result = *(vip) ((addr << 5) + T2_IO + 0x00);
0367     return __kernel_extbl(result, addr & 3);
0368 }
0369
0370 extern inline void t2_outb(u8 b, unsigned long addr)
0371 {
0372     unsigned long w;
0373
0374     w = __kernel_insbl(b, addr & 3);
0375     *(vuip) ((addr << 5) + T2_IO + 0x00) = w;
0376     mb();
0377 }
0378
0379 extern inline u16 t2_inw(unsigned long addr)
0380 {
0381     long result = *(vip) ((addr << 5) + T2_IO + 0x08);
0382     return __kernel_extwl(result, addr & 3);
0383 }
0384
0385 extern inline void t2_outw(u16 b, unsigned long addr)
0386 {
0387     unsigned long w;
0388
0389     w = __kernel_inswl(b, addr & 3);
0390     *(vuip) ((addr << 5) + T2_IO + 0x08) = w;
0391     mb();
0392 }
0393
0394 extern inline u32 t2_inl(unsigned long addr)
0395 {
0396     return *(vuip) ((addr << 5) + T2_IO + 0x18);
0397 }
0398
0399 extern inline void t2_outl(u32 b, unsigned long addr)
0400 {
0401     *(vuip) ((addr << 5) + T2_IO + 0x18) = b;
0402     mb();
0403 }
0404
0405
0406 /*
0407  * Memory functions.
0408  *
0409  * For reading and writing 8 and 16 bit quantities we need to
0410  * go through one of the three sparse address mapping regions
0411  * and use the HAE_MEM CSR to provide some bits of the address.
0412  * The following few routines use only sparse address region 1
0413  * which gives 1Gbyte of accessible space which relates exactly
0414  * to the amount of PCI memory mapping *into* system address space.
0415  * See p 6-17 of the specification but it looks something like this:
0416  *
0417  * 21164 Address:
0418  *
0419  *          3         2         1
0420  * 9876543210987654321098765432109876543210
0421  * 1ZZZZ0.PCI.QW.Address............BBLL
0422  *
0423  * ZZ = SBZ
0424  * BB = Byte offset
0425  * LL = Transfer length
0426  *
0427  * PCI Address:
0428  *
0429  * 3         2         1
0430  * 10987654321098765432109876543210
0431  * HHH....PCI.QW.Address........ 00
0432  *
0433  * HHH = 31:29 HAE_MEM CSR
0434  *
0435  */
0436
0437 #ifdef T2_ONE_HAE_WINDOW
0438 #define t2_set_hae
0439 #else
0440 #define t2_set_hae { \
0441     unsigned long msb = addr >> 27; \
0442     addr &= T2_MEM_R1_MASK; \
0443     set_hae(msb); \
0444 }
0445 #endif
0446
0447 /*
0448  * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since
0449  *       they may be called directly, rather than through the
0450  *       ioreadNN/iowriteNN routines.
0451  */
0452
0453 __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr)
0454 {
0455     unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
0456     unsigned long result;
0457
0458     t2_set_hae;
0459
0460     result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
0461     return __kernel_extbl(result, addr & 3);
0462 }
0463
0464 __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr)
0465 {
0466     unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
0467     unsigned long result;
0468
0469     t2_set_hae;
0470
0471     result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
0472     return __kernel_extwl(result, addr & 3);
0473 }
0474
0475 /*
0476  * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
0477  * because we cannot access all of DENSE without changing its HAE.
0478  */
0479 __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr)
0480 {
0481     unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
0482     unsigned long result;
0483
0484     t2_set_hae;
0485
0486     result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
0487     return result & 0xffffffffUL;
0488 }
0489
0490 __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr)
0491 {
0492     unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
0493     unsigned long r0, r1, work;
0494
0495     t2_set_hae;
0496
0497     work = (addr << 5) + T2_SPARSE_MEM + 0x18;
0498     r0 = *(vuip)(work);
0499     r1 = *(vuip)(work + (4 << 5));
0500     return r1 << 32 | r0;
0501 }
0502
0503 __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr)
0504 {
0505     unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
0506     unsigned long w;
0507
0508     t2_set_hae;
0509
0510     w = __kernel_insbl(b, addr & 3);
0511     *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
0512 }
0513
0514 __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr)
0515 {
0516     unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
0517     unsigned long w;
0518
0519     t2_set_hae;
0520
0521     w = __kernel_inswl(b, addr & 3);
0522     *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
0523 }
0524
0525 /*
0526  * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
0527  * because we cannot access all of DENSE without changing its HAE.
0528  */
0529 __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr)
0530 {
0531     unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
0532
0533     t2_set_hae;
0534
0535     *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
0536 }
0537
0538 __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr)
0539 {
0540     unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
0541     unsigned long work;
0542
0543     t2_set_hae;
0544
0545     work = (addr << 5) + T2_SPARSE_MEM + 0x18;
0546     *(vuip)work = b;
0547     *(vuip)(work + (4 << 5)) = b >> 32;
0548 }
0549
0550 __EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr)
0551 {
0552     return (void __iomem *)(addr + T2_IO);
0553 }
0554
0555 __EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr,
0556                      unsigned long size)
0557 {
0558     return (void __iomem *)(addr + T2_DENSE_MEM);
0559 }
0560
0561 __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
0562 {
0563     return (long)addr >= 0;
0564 }
0565
0566 __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr)
0567 {
0568     return (unsigned long)addr >= T2_DENSE_MEM;
0569 }
0570
0571 /* New-style ioread interface.  The mmio routines are so ugly for T2 that
0572    it doesn't make sense to merge the pio and mmio routines.  */
0573
0574 #define IOPORT(OS, NS)                          \
0575 __EXTERN_INLINE unsigned int t2_ioread##NS(const void __iomem *xaddr)       \
0576 {                                   \
0577     if (t2_is_mmio(xaddr))                      \
0578         return t2_read##OS(xaddr);              \
0579     else                                \
0580         return t2_in##OS((unsigned long)xaddr - T2_IO);     \
0581 }                                   \
0582 __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr)   \
0583 {                                   \
0584     if (t2_is_mmio(xaddr))                      \
0585         t2_write##OS(b, xaddr);                 \
0586     else                                \
0587         t2_out##OS(b, (unsigned long)xaddr - T2_IO);        \
0588 }
0589
0590 IOPORT(b, 8)
0591 IOPORT(w, 16)
0592 IOPORT(l, 32)
0593
0594 #undef IOPORT
0595
0596 #undef vip
0597 #undef vuip
0598
0599 #undef __IO_PREFIX
0600 #define __IO_PREFIX     t2
0601 #define t2_trivial_rw_bw    0
0602 #define t2_trivial_rw_lq    0
0603 #define t2_trivial_io_bw    0
0604 #define t2_trivial_io_lq    0
0605 #define t2_trivial_iounmap  1
0606 #include <asm/io_trivial.h>
0607
0608 #ifdef __IO_EXTERN_INLINE
0609 #undef __EXTERN_INLINE
0610 #undef __IO_EXTERN_INLINE
0611 #endif
0612
0613 #endif /* __KERNEL__ */
0614
0615 #endif /* __ALPHA_T2__H__ */