include/asm/core_polaris.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_POLARIS__H__
0003 #define __ALPHA_POLARIS__H__
0004
0005 #include <linux/types.h>
0006 #include <asm/compiler.h>
0007
0008 /*
0009  * POLARIS is the internal name for a core logic chipset which provides
0010  * memory controller and PCI access for the 21164PC chip based systems.
0011  *
0012  * This file is based on:
0013  *
0014  * Polaris System Controller
0015  * Device Functional Specification
0016  * 22-Jan-98
0017  * Rev. 4.2
0018  *
0019  */
0020
0021 /* Polaris memory regions */
0022 #define POLARIS_SPARSE_MEM_BASE     (IDENT_ADDR + 0xf800000000UL)
0023 #define POLARIS_DENSE_MEM_BASE      (IDENT_ADDR + 0xf900000000UL)
0024 #define POLARIS_SPARSE_IO_BASE      (IDENT_ADDR + 0xf980000000UL)
0025 #define POLARIS_SPARSE_CONFIG_BASE  (IDENT_ADDR + 0xf9c0000000UL)
0026 #define POLARIS_IACK_BASE       (IDENT_ADDR + 0xf9f8000000UL)
0027 #define POLARIS_DENSE_IO_BASE       (IDENT_ADDR + 0xf9fc000000UL)
0028 #define POLARIS_DENSE_CONFIG_BASE   (IDENT_ADDR + 0xf9fe000000UL)
0029
0030 #define POLARIS_IACK_SC         POLARIS_IACK_BASE
0031
0032 /* The Polaris command/status registers live in PCI Config space for
0033  * bus 0/device 0.  As such, they may be bytes, words, or doublewords.
0034  */
0035 #define POLARIS_W_VENID     (POLARIS_DENSE_CONFIG_BASE)
0036 #define POLARIS_W_DEVID     (POLARIS_DENSE_CONFIG_BASE+2)
0037 #define POLARIS_W_CMD       (POLARIS_DENSE_CONFIG_BASE+4)
0038 #define POLARIS_W_STATUS    (POLARIS_DENSE_CONFIG_BASE+6)
0039
0040 /*
0041  * Data structure for handling POLARIS machine checks:
0042  */
0043 struct el_POLARIS_sysdata_mcheck {
0044     u_long      psc_status;
0045     u_long  psc_pcictl0;
0046     u_long  psc_pcictl1;
0047     u_long  psc_pcictl2;
0048 };
0049
0050 #ifdef __KERNEL__
0051
0052 #ifndef __EXTERN_INLINE
0053 #define __EXTERN_INLINE extern inline
0054 #define __IO_EXTERN_INLINE
0055 #endif
0056
0057 /*
0058  * I/O functions:
0059  *
0060  * POLARIS, the PCI/memory support chipset for the PCA56 (21164PC)
0061  * processors, can use either a sparse address  mapping scheme, or the
0062  * so-called byte-word PCI address space, to get at PCI memory and I/O.
0063  *
0064  * However, we will support only the BWX form.
0065  */
0066
0067 /*
0068  * Memory functions.  Polaris allows all accesses (byte/word
0069  * as well as long/quad) to be done through dense space.
0070  *
0071  * We will only support DENSE access via BWX insns.
0072  */
0073
0074 __EXTERN_INLINE void __iomem *polaris_ioportmap(unsigned long addr)
0075 {
0076     return (void __iomem *)(addr + POLARIS_DENSE_IO_BASE);
0077 }
0078
0079 __EXTERN_INLINE void __iomem *polaris_ioremap(unsigned long addr,
0080                           unsigned long size)
0081 {
0082     return (void __iomem *)(addr + POLARIS_DENSE_MEM_BASE);
0083 }
0084
0085 __EXTERN_INLINE int polaris_is_ioaddr(unsigned long addr)
0086 {
0087     return addr >= POLARIS_SPARSE_MEM_BASE;
0088 }
0089
0090 __EXTERN_INLINE int polaris_is_mmio(const volatile void __iomem *addr)
0091 {
0092     return (unsigned long)addr < POLARIS_SPARSE_IO_BASE;
0093 }
0094
0095 #undef __IO_PREFIX
0096 #define __IO_PREFIX     polaris
0097 #define polaris_trivial_rw_bw   1
0098 #define polaris_trivial_rw_lq   1
0099 #define polaris_trivial_io_bw   1
0100 #define polaris_trivial_io_lq   1
0101 #define polaris_trivial_iounmap 1
0102 #include <asm/io_trivial.h>
0103
0104 #ifdef __IO_EXTERN_INLINE
0105 #undef __EXTERN_INLINE
0106 #undef __IO_EXTERN_INLINE
0107 #endif
0108
0109 #endif /* __KERNEL__ */
0110
0111 #endif /* __ALPHA_POLARIS__H__ */