include/asm/core_mcpcia.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_MCPCIA__H__
0003 #define __ALPHA_MCPCIA__H__
0004
0005 /* Define to experiment with fitting everything into one 128MB HAE window.
0006    One window per bus, that is.  */
0007 #define MCPCIA_ONE_HAE_WINDOW 1
0008
0009 #include <linux/types.h>
0010 #include <asm/compiler.h>
0011 #include <asm/mce.h>
0012
0013 /*
0014  * MCPCIA is the internal name for a core logic chipset which provides
0015  * PCI access for the RAWHIDE family of systems.
0016  *
0017  * This file is based on:
0018  *
0019  * RAWHIDE System Programmer's Manual
0020  * 16-May-96
0021  * Rev. 1.4
0022  *
0023  */
0024
0025 /*------------------------------------------------------------------------**
0026 **                                                                        **
0027 **  I/O procedures                                                        **
0028 **                                                                        **
0029 **      inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers             **
0030 **  inportbxt: 8 bits only                                            **
0031 **      inport:    alias of inportw                                       **
0032 **      outport:   alias of outportw                                      **
0033 **                                                                        **
0034 **      inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers       **
0035 **  inmembxt: 8 bits only                                             **
0036 **      inmem:    alias of inmemw                                         **
0037 **      outmem:   alias of outmemw                                        **
0038 **                                                                        **
0039 **------------------------------------------------------------------------*/
0040
0041
0042 /* MCPCIA ADDRESS BIT DEFINITIONS
0043  *
0044  *  3333 3333 3322 2222 2222 1111 1111 11
0045  *  9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
0046  *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
0047  *  1                                             000
0048  *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
0049  *  |                                             |\|
0050  *  |                               Byte Enable --+ |
0051  *  |                             Transfer Length --+
0052  *  +-- IO space, not cached
0053  *
0054  *   Byte      Transfer
0055  *   Enable    Length    Transfer  Byte    Address
0056  *   adr<6:5>  adr<4:3>  Length    Enable  Adder
0057  *   ---------------------------------------------
0058  *      00        00      Byte      1110   0x000
0059  *      01        00      Byte      1101   0x020
0060  *      10        00      Byte      1011   0x040
0061  *      11        00      Byte      0111   0x060
0062  *
0063  *      00        01      Word      1100   0x008
0064  *      01        01      Word      1001   0x028 <= Not supported in this code.
0065  *      10        01      Word      0011   0x048
0066  *
0067  *      00        10      Tribyte   1000   0x010
0068  *      01        10      Tribyte   0001   0x030
0069  *
0070  *      10        11      Longword  0000   0x058
0071  *
0072  *      Note that byte enables are asserted low.
0073  *
0074  */
0075
0076 #define MCPCIA_MAX_HOSES 4
0077
0078 #define MCPCIA_MID(m)       ((unsigned long)(m) << 33)
0079
0080 /* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
0081    Durango adds PCI2 and PCI3 at MID 6 and 7 respectively.  */
0082 #define MCPCIA_HOSE2MID(h)  ((h) + 4)
0083
0084 #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
0085
0086 /*
0087  * Memory spaces:
0088  */
0089 #define MCPCIA_SPARSE(m)    (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
0090 #define MCPCIA_DENSE(m)     (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
0091 #define MCPCIA_IO(m)        (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
0092 #define MCPCIA_CONF(m)      (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
0093 #define MCPCIA_CSR(m)       (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
0094 #define MCPCIA_IO_IACK(m)   (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
0095 #define MCPCIA_DENSE_IO(m)  (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
0096 #define MCPCIA_DENSE_CONF(m)    (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
0097
0098 /*
0099  *  General Registers
0100  */
0101 #define MCPCIA_REV(m)       (MCPCIA_CSR(m) + 0x000)
0102 #define MCPCIA_WHOAMI(m)    (MCPCIA_CSR(m) + 0x040)
0103 #define MCPCIA_PCI_LAT(m)   (MCPCIA_CSR(m) + 0x080)
0104 #define MCPCIA_CAP_CTRL(m)  (MCPCIA_CSR(m) + 0x100)
0105 #define MCPCIA_HAE_MEM(m)   (MCPCIA_CSR(m) + 0x400)
0106 #define MCPCIA_HAE_IO(m)    (MCPCIA_CSR(m) + 0x440)
0107 #define _MCPCIA_IACK_SC(m)  (MCPCIA_CSR(m) + 0x480)
0108 #define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0)
0109
0110 /*
0111  * Interrupt Control registers
0112  */
0113 #define MCPCIA_INT_CTL(m)   (MCPCIA_CSR(m) + 0x500)
0114 #define MCPCIA_INT_REQ(m)   (MCPCIA_CSR(m) + 0x540)
0115 #define MCPCIA_INT_TARG(m)  (MCPCIA_CSR(m) + 0x580)
0116 #define MCPCIA_INT_ADR(m)   (MCPCIA_CSR(m) + 0x5C0)
0117 #define MCPCIA_INT_ADR_EXT(m)   (MCPCIA_CSR(m) + 0x600)
0118 #define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640)
0119 #define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680)
0120 #define MCPCIA_INT_ACK0(m)  (MCPCIA_CSR(m) + 0x10003f00)
0121 #define MCPCIA_INT_ACK1(m)  (MCPCIA_CSR(m) + 0x10003f40)
0122
0123 /*
0124  * Performance Monitor registers
0125  */
0126 #define MCPCIA_PERF_MON(m)  (MCPCIA_CSR(m) + 0x300)
0127 #define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340)
0128
0129 /*
0130  * Diagnostic Registers
0131  */
0132 #define MCPCIA_CAP_DIAG(m)  (MCPCIA_CSR(m) + 0x700)
0133 #define MCPCIA_TOP_OF_MEM(m)    (MCPCIA_CSR(m) + 0x7C0)
0134
0135 /*
0136  * Error registers
0137  */
0138 #define MCPCIA_MC_ERR0(m)   (MCPCIA_CSR(m) + 0x800)
0139 #define MCPCIA_MC_ERR1(m)   (MCPCIA_CSR(m) + 0x840)
0140 #define MCPCIA_CAP_ERR(m)   (MCPCIA_CSR(m) + 0x880)
0141 #define MCPCIA_PCI_ERR1(m)  (MCPCIA_CSR(m) + 0x1040)
0142 #define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000)
0143 #define MCPCIA_MDPA_SYN(m)  (MCPCIA_CSR(m) + 0x4040)
0144 #define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080)
0145 #define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000)
0146 #define MCPCIA_MDPB_SYN(m)  (MCPCIA_CSR(m) + 0x8040)
0147 #define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080)
0148
0149 /*
0150  * PCI Address Translation Registers.
0151  */
0152 #define MCPCIA_SG_TBIA(m)   (MCPCIA_CSR(m) + 0x1300)
0153 #define MCPCIA_HBASE(m)     (MCPCIA_CSR(m) + 0x1340)
0154
0155 #define MCPCIA_W0_BASE(m)   (MCPCIA_CSR(m) + 0x1400)
0156 #define MCPCIA_W0_MASK(m)   (MCPCIA_CSR(m) + 0x1440)
0157 #define MCPCIA_T0_BASE(m)   (MCPCIA_CSR(m) + 0x1480)
0158
0159 #define MCPCIA_W1_BASE(m)   (MCPCIA_CSR(m) + 0x1500)
0160 #define MCPCIA_W1_MASK(m)   (MCPCIA_CSR(m) + 0x1540)
0161 #define MCPCIA_T1_BASE(m)   (MCPCIA_CSR(m) + 0x1580)
0162
0163 #define MCPCIA_W2_BASE(m)   (MCPCIA_CSR(m) + 0x1600)
0164 #define MCPCIA_W2_MASK(m)   (MCPCIA_CSR(m) + 0x1640)
0165 #define MCPCIA_T2_BASE(m)   (MCPCIA_CSR(m) + 0x1680)
0166
0167 #define MCPCIA_W3_BASE(m)   (MCPCIA_CSR(m) + 0x1700)
0168 #define MCPCIA_W3_MASK(m)   (MCPCIA_CSR(m) + 0x1740)
0169 #define MCPCIA_T3_BASE(m)   (MCPCIA_CSR(m) + 0x1780)
0170
0171 /* Hack!  Only words for bus 0.  */
0172
0173 #ifndef MCPCIA_ONE_HAE_WINDOW
0174 #define MCPCIA_HAE_ADDRESS  MCPCIA_HAE_MEM(4)
0175 #endif
0176 #define MCPCIA_IACK_SC      _MCPCIA_IACK_SC(4)
0177
0178 /*
0179  * The canonical non-remaped I/O and MEM addresses have these values
0180  * subtracted out.  This is arranged so that folks manipulating ISA
0181  * devices can use their familiar numbers and have them map to bus 0.
0182  */
0183
0184 #define MCPCIA_IO_BIAS      MCPCIA_IO(4)
0185 #define MCPCIA_MEM_BIAS     MCPCIA_DENSE(4)
0186
0187 /* Offset between ram physical addresses and pci64 DAC bus addresses.  */
0188 #define MCPCIA_DAC_OFFSET   (1UL << 40)
0189
0190 /*
0191  * Data structure for handling MCPCIA machine checks:
0192  */
0193 struct el_MCPCIA_uncorrected_frame_mcheck {
0194     struct el_common header;
0195     struct el_common_EV5_uncorrectable_mcheck procdata;
0196 };
0197
0198
0199 #ifdef __KERNEL__
0200
0201 #ifndef __EXTERN_INLINE
0202 #define __EXTERN_INLINE extern inline
0203 #define __IO_EXTERN_INLINE
0204 #endif
0205
0206 /*
0207  * I/O functions:
0208  *
0209  * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
0210  * and EV56 (21164a) processors, can use either a sparse address mapping
0211  * scheme, or the so-called byte-word PCI address space, to get at PCI memory
0212  * and I/O.
0213  *
0214  * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
0215  */
0216
0217 /*
0218  * Memory functions.  64-bit and 32-bit accesses are done through
0219  * dense memory space, everything else through sparse space.
0220  *
0221  * For reading and writing 8 and 16 bit quantities we need to
0222  * go through one of the three sparse address mapping regions
0223  * and use the HAE_MEM CSR to provide some bits of the address.
0224  * The following few routines use only sparse address region 1
0225  * which gives 1Gbyte of accessible space which relates exactly
0226  * to the amount of PCI memory mapping *into* system address space.
0227  * See p 6-17 of the specification but it looks something like this:
0228  *
0229  * 21164 Address:
0230  *
0231  *          3         2         1
0232  * 9876543210987654321098765432109876543210
0233  * 1ZZZZ0.PCI.QW.Address............BBLL
0234  *
0235  * ZZ = SBZ
0236  * BB = Byte offset
0237  * LL = Transfer length
0238  *
0239  * PCI Address:
0240  *
0241  * 3         2         1
0242  * 10987654321098765432109876543210
0243  * HHH....PCI.QW.Address........ 00
0244  *
0245  * HHH = 31:29 HAE_MEM CSR
0246  *
0247  */
0248
0249 #define vip volatile int __force *
0250 #define vuip    volatile unsigned int __force *
0251
0252 #ifndef MCPCIA_ONE_HAE_WINDOW
0253 #define MCPCIA_FROB_MMIO                        \
0254     if (__mcpcia_is_mmio(hose)) {                   \
0255         set_hae(hose & 0xffffffff);             \
0256         hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);   \
0257     }
0258 #else
0259 #define MCPCIA_FROB_MMIO                        \
0260     if (__mcpcia_is_mmio(hose)) {                   \
0261         hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);   \
0262     }
0263 #endif
0264
0265 extern inline int __mcpcia_is_mmio(unsigned long addr)
0266 {
0267     return (addr & 0x80000000UL) == 0;
0268 }
0269
0270 __EXTERN_INLINE unsigned int mcpcia_ioread8(const void __iomem *xaddr)
0271 {
0272     unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
0273     unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
0274     unsigned long result;
0275
0276     MCPCIA_FROB_MMIO;
0277
0278     result = *(vip) ((addr << 5) + hose + 0x00);
0279     return __kernel_extbl(result, addr & 3);
0280 }
0281
0282 __EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
0283 {
0284     unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
0285     unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
0286     unsigned long w;
0287
0288     MCPCIA_FROB_MMIO;
0289
0290     w = __kernel_insbl(b, addr & 3);
0291     *(vuip) ((addr << 5) + hose + 0x00) = w;
0292 }
0293
0294 __EXTERN_INLINE unsigned int mcpcia_ioread16(const void __iomem *xaddr)
0295 {
0296     unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
0297     unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
0298     unsigned long result;
0299
0300     MCPCIA_FROB_MMIO;
0301
0302     result = *(vip) ((addr << 5) + hose + 0x08);
0303     return __kernel_extwl(result, addr & 3);
0304 }
0305
0306 __EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
0307 {
0308     unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
0309     unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
0310     unsigned long w;
0311
0312     MCPCIA_FROB_MMIO;
0313
0314     w = __kernel_inswl(b, addr & 3);
0315     *(vuip) ((addr << 5) + hose + 0x08) = w;
0316 }
0317
0318 __EXTERN_INLINE unsigned int mcpcia_ioread32(const void __iomem *xaddr)
0319 {
0320     unsigned long addr = (unsigned long)xaddr;
0321
0322     if (!__mcpcia_is_mmio(addr))
0323         addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
0324
0325     return *(vuip)addr;
0326 }
0327
0328 __EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
0329 {
0330     unsigned long addr = (unsigned long)xaddr;
0331
0332     if (!__mcpcia_is_mmio(addr))
0333         addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
0334
0335     *(vuip)addr = b;
0336 }
0337
0338
0339 __EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
0340 {
0341     return (void __iomem *)(addr + MCPCIA_IO_BIAS);
0342 }
0343
0344 __EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr,
0345                          unsigned long size)
0346 {
0347     return (void __iomem *)(addr + MCPCIA_MEM_BIAS);
0348 }
0349
0350 __EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
0351 {
0352     return addr >= MCPCIA_SPARSE(0);
0353 }
0354
0355 __EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
0356 {
0357     unsigned long addr = (unsigned long) xaddr;
0358     return __mcpcia_is_mmio(addr);
0359 }
0360
0361 #undef MCPCIA_FROB_MMIO
0362
0363 #undef vip
0364 #undef vuip
0365
0366 #undef __IO_PREFIX
0367 #define __IO_PREFIX     mcpcia
0368 #define mcpcia_trivial_rw_bw    2
0369 #define mcpcia_trivial_rw_lq    1
0370 #define mcpcia_trivial_io_bw    0
0371 #define mcpcia_trivial_io_lq    0
0372 #define mcpcia_trivial_iounmap  1
0373 #include <asm/io_trivial.h>
0374
0375 #ifdef __IO_EXTERN_INLINE
0376 #undef __EXTERN_INLINE
0377 #undef __IO_EXTERN_INLINE
0378 #endif
0379
0380 #endif /* __KERNEL__ */
0381
0382 #endif /* __ALPHA_MCPCIA__H__ */