include/asm/core_irongate.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_IRONGATE__H__
0003 #define __ALPHA_IRONGATE__H__
0004
0005 #include <linux/types.h>
0006 #include <asm/compiler.h>
0007
0008 /*
0009  * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
0010  * which provides memory controller and PCI access for NAUTILUS-based
0011  * EV6 (21264) systems.
0012  *
0013  * This file is based on:
0014  *
0015  * IronGate management library, (c) 1999 Alpha Processor, Inc.
0016  * Copyright (C) 1999 Alpha Processor, Inc.,
0017  *  (David Daniel, Stig Telfer, Soohoon Lee)
0018  */
0019
0020 /*
0021  * The 21264 supports, and internally recognizes, a 44-bit physical
0022  * address space that is divided equally between memory address space
0023  * and I/O address space. Memory address space resides in the lower
0024  * half of the physical address space (PA[43]=0) and I/O address space
0025  * resides in the upper half of the physical address space (PA[43]=1).
0026  */
0027
0028 /*
0029  * Irongate CSR map.  Some of the CSRs are 8 or 16 bits, but all access
0030  * through the routines given is 32-bit.
0031  *
0032  * The first 0x40 bytes are standard as per the PCI spec.
0033  */
0034
0035 typedef volatile __u32  igcsr32;
0036
0037 typedef struct {
0038     igcsr32 dev_vendor;     /* 0x00 - device ID, vendor ID */
0039     igcsr32 stat_cmd;       /* 0x04 - status, command */
0040     igcsr32 class;          /* 0x08 - class code, rev ID */
0041     igcsr32 latency;        /* 0x0C - header type, PCI latency */
0042     igcsr32 bar0;           /* 0x10 - BAR0 - AGP */
0043     igcsr32 bar1;           /* 0x14 - BAR1 - GART */
0044     igcsr32 bar2;           /* 0x18 - Power Management reg block */
0045
0046     igcsr32 rsrvd0[6];      /* 0x1C-0x33 reserved */
0047
0048     igcsr32 capptr;         /* 0x34 - Capabilities pointer */
0049
0050     igcsr32 rsrvd1[2];      /* 0x38-0x3F reserved */
0051
0052     igcsr32 bacsr10;        /* 0x40 - base address chip selects */
0053     igcsr32 bacsr32;        /* 0x44 - base address chip selects */
0054     igcsr32 bacsr54_eccms761;   /* 0x48 - 751: base addr. chip selects
0055                           761: ECC, mode/status */
0056
0057     igcsr32 rsrvd2[1];      /* 0x4C-0x4F reserved */
0058
0059     igcsr32 drammap;        /* 0x50 - address mapping control */
0060     igcsr32 dramtm;         /* 0x54 - timing, driver strength */
0061     igcsr32 dramms;         /* 0x58 - DRAM mode/status */
0062
0063     igcsr32 rsrvd3[1];      /* 0x5C-0x5F reserved */
0064
0065     igcsr32 biu0;           /* 0x60 - bus interface unit */
0066     igcsr32 biusip;         /* 0x64 - Serial initialisation pkt */
0067
0068     igcsr32 rsrvd4[2];      /* 0x68-0x6F reserved */
0069
0070     igcsr32 mro;            /* 0x70 - memory request optimiser */
0071
0072     igcsr32 rsrvd5[3];      /* 0x74-0x7F reserved */
0073
0074     igcsr32 whami;          /* 0x80 - who am I */
0075     igcsr32 pciarb;         /* 0x84 - PCI arbitration control */
0076     igcsr32 pcicfg;         /* 0x88 - PCI config status */
0077
0078     igcsr32 rsrvd6[4];      /* 0x8C-0x9B reserved */
0079
0080     igcsr32 pci_mem;        /* 0x9C - PCI top of memory,
0081                           761 only */
0082
0083     /* AGP (bus 1) control registers */
0084     igcsr32 agpcap;         /* 0xA0 - AGP Capability Identifier */
0085     igcsr32 agpstat;        /* 0xA4 - AGP status register */
0086     igcsr32 agpcmd;         /* 0xA8 - AGP control register */
0087     igcsr32 agpva;          /* 0xAC - AGP Virtual Address Space */
0088     igcsr32 agpmode;        /* 0xB0 - AGP/GART mode control */
0089 } Irongate0;
0090
0091
0092 typedef struct {
0093
0094     igcsr32 dev_vendor;     /* 0x00 - Device and Vendor IDs */
0095     igcsr32 stat_cmd;       /* 0x04 - Status and Command regs */
0096     igcsr32 class;          /* 0x08 - subclass, baseclass etc */
0097     igcsr32 htype;          /* 0x0C - header type (at 0x0E) */
0098     igcsr32 rsrvd0[2];      /* 0x10-0x17 reserved */
0099     igcsr32 busnos;         /* 0x18 - Primary, secondary bus nos */
0100     igcsr32 io_baselim_regs;    /* 0x1C - IO base, IO lim, AGP status */
0101     igcsr32 mem_baselim;        /* 0x20 - memory base, memory lim */
0102     igcsr32 pfmem_baselim;      /* 0x24 - prefetchable base, lim */
0103     igcsr32 rsrvd1[2];      /* 0x28-0x2F reserved */
0104     igcsr32 io_baselim;     /* 0x30 - IO base, IO limit */
0105     igcsr32 rsrvd2[2];      /* 0x34-0x3B - reserved */
0106     igcsr32 interrupt;      /* 0x3C - interrupt, PCI bridge ctrl */
0107
0108 } Irongate1;
0109
0110 extern igcsr32 *IronECC;
0111
0112 /*
0113  * Memory spaces:
0114  */
0115
0116 /* Irongate is consistent with a subset of the Tsunami memory map */
0117 #ifdef USE_48_BIT_KSEG
0118 #define IRONGATE_BIAS 0x80000000000UL
0119 #else
0120 #define IRONGATE_BIAS 0x10000000000UL
0121 #endif
0122
0123
0124 #define IRONGATE_MEM        (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
0125 #define IRONGATE_IACK_SC    (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
0126 #define IRONGATE_IO     (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
0127 #define IRONGATE_CONF       (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
0128
0129 /*
0130  * PCI Configuration space accesses are formed like so:
0131  *
0132  * 0x1FE << 24 |  : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
0133  *                : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
0134  *                  ---bus numer---   -device-- -fun-   ---register----
0135  */
0136
0137 #define IGCSR(dev,fun,reg)  ( IRONGATE_CONF | \
0138                 ((dev)<<11) | \
0139                 ((fun)<<8) | \
0140                 (reg) )
0141
0142 #define IRONGATE0       ((Irongate0 *) IGCSR(0, 0, 0))
0143 #define IRONGATE1       ((Irongate1 *) IGCSR(1, 0, 0))
0144
0145 /*
0146  * Data structure for handling IRONGATE machine checks:
0147  * This is the standard OSF logout frame
0148  */
0149
0150 #define SCB_Q_SYSERR    0x620           /* OSF definitions */
0151 #define SCB_Q_PROCERR   0x630
0152 #define SCB_Q_SYSMCHK   0x660
0153 #define SCB_Q_PROCMCHK  0x670
0154
0155 struct el_IRONGATE_sysdata_mcheck {
0156     __u32 FrameSize;                 /* Bytes, including this field */
0157     __u32 FrameFlags;                /* <31> = Retry, <30> = Second Error */
0158     __u32 CpuOffset;                 /* Offset to CPU-specific into */
0159     __u32 SystemOffset;              /* Offset to system-specific info */
0160     __u32 MCHK_Code;
0161     __u32 MCHK_Frame_Rev;
0162     __u64 I_STAT;
0163     __u64 DC_STAT;
0164     __u64 C_ADDR;
0165     __u64 DC1_SYNDROME;
0166     __u64 DC0_SYNDROME;
0167     __u64 C_STAT;
0168     __u64 C_STS;
0169     __u64 RESERVED0;
0170     __u64 EXC_ADDR;
0171     __u64 IER_CM;
0172     __u64 ISUM;
0173     __u64 MM_STAT;
0174     __u64 PAL_BASE;
0175     __u64 I_CTL;
0176     __u64 PCTX;
0177 };
0178
0179
0180 #ifdef __KERNEL__
0181
0182 #ifndef __EXTERN_INLINE
0183 #define __EXTERN_INLINE extern inline
0184 #define __IO_EXTERN_INLINE
0185 #endif
0186
0187 /*
0188  * I/O functions:
0189  *
0190  * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
0191  * K7 can only use linear accesses to get at PCI memory and I/O spaces.
0192  */
0193
0194 /*
0195  * Memory functions.  All accesses are done through linear space.
0196  */
0197
0198 __EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr)
0199 {
0200     return (void __iomem *)(addr + IRONGATE_IO);
0201 }
0202
0203 extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size);
0204 extern void irongate_iounmap(volatile void __iomem *addr);
0205
0206 __EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
0207 {
0208     return addr >= IRONGATE_MEM;
0209 }
0210
0211 __EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr)
0212 {
0213     unsigned long addr = (unsigned long)xaddr;
0214     return addr < IRONGATE_IO || addr >= IRONGATE_CONF;
0215 }
0216
0217 #undef __IO_PREFIX
0218 #define __IO_PREFIX         irongate
0219 #define irongate_trivial_rw_bw      1
0220 #define irongate_trivial_rw_lq      1
0221 #define irongate_trivial_io_bw      1
0222 #define irongate_trivial_io_lq      1
0223 #define irongate_trivial_iounmap    0
0224 #include <asm/io_trivial.h>
0225
0226 #ifdef __IO_EXTERN_INLINE
0227 #undef __EXTERN_INLINE
0228 #undef __IO_EXTERN_INLINE
0229 #endif
0230
0231 #endif /* __KERNEL__ */
0232
0233 #endif /* __ALPHA_IRONGATE__H__ */