include/asm/core_apecs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ALPHA_APECS__H__
0003 #define __ALPHA_APECS__H__
0004
0005 #include <linux/types.h>
0006 #include <asm/compiler.h>
0007
0008 /*
0009  * APECS is the internal name for the 2107x chipset which provides
0010  * memory controller and PCI access for the 21064 chip based systems.
0011  *
0012  * This file is based on:
0013  *
0014  * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
0015  * Data Sheet
0016  *
0017  * EC-N0648-72
0018  *
0019  *
0020  * david.rusling@reo.mts.dec.com Initial Version.
0021  *
0022  */
0023
0024 /*
0025    An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
0026    that get passed through the PCI<->ISA bridge chip. So we've gotta use
0027    both windows to max out the physical memory we can DMA to. Sigh...
0028
0029    If we try a window at 0 for 1GB as a work-around, we run into conflicts
0030    with ISA/PCI bus memory which can't be relocated, like VGA aperture and
0031    BIOS ROMs. So we must put the windows high enough to avoid these areas.
0032
0033    We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1,
0034    and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1.
0035    Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually
0036    be used for that range (via virt_to_bus()).
0037
0038    Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb,
0039    to keep virt_to_bus() from returning an address in the first window, for
0040    a data area that goes beyond the 64Mb first DMA window.  Sigh...
0041    The fudge factor MUST match with <asm/dma.h> MAX_DMA_ADDRESS, but
0042    we can't just use that here, because of header file looping... :-(
0043
0044    Window 1 will be used for all DMA from the ISA bus; yes, that does
0045    limit what memory an ISA floppy or sound card or Ethernet can touch, but
0046    it's also a known limitation on other platforms as well. We use the
0047    same technique that is used on INTEL platforms with similar limitation:
0048    set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init().
0049    We trust that any ISA bus device drivers will *always* ask for DMAable
0050    memory explicitly via kmalloc()/get_free_pages() flags arguments.
0051
0052    Note that most PCI bus devices' drivers do *not* explicitly ask for
0053    DMAable memory; they count on being able to DMA to any memory they
0054    get from kmalloc()/get_free_pages(). They will also use window 1 for
0055    any physical memory accesses below 64Mb; the rest will be handled by
0056    window 2, maxing out at 1Gb of memory. I trust this is enough... :-)
0057
0058    We hope that the area before the first window is large enough so that
0059    there will be no overlap at the top end (64Mb). We *must* locate the
0060    PCI cards' memory just below window 1, so that there's still the
0061    possibility of being able to access it via SPARSE space. This is
0062    important for cards such as the Matrox Millennium, whose Xserver
0063    wants to access memory-mapped registers in byte and short lengths.
0064
0065    Note that the XL is treated differently from the AVANTI, even though
0066    for most other things they are identical. It didn't seem reasonable to
0067    make the AVANTI support pay for the limitations of the XL. It is true,
0068    however, that an XL kernel will run on an AVANTI without problems.
0069
0070    %%% All of this should be obviated by the ability to route
0071    everything through the iommu.
0072 */
0073
0074 /*
0075  * 21071-DA Control and Status registers.
0076  * These are used for PCI memory access.
0077  */
0078 #define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)
0079 #define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)
0080 #define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)
0081 #define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)
0082 #define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)
0083 #define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)
0084
0085 #define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)
0086 #define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)
0087
0088 #define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)
0089 #define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)
0090
0091 #define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)
0092 #define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)
0093
0094 #define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)
0095 #define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)
0096 #define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)
0097
0098 #define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)
0099
0100 #define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)
0101 #define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)
0102 #define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)
0103 #define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)
0104 #define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)
0105 #define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)
0106 #define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)
0107 #define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)
0108
0109 #define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)
0110 #define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)
0111 #define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)
0112 #define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)
0113 #define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)
0114 #define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)
0115 #define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)
0116 #define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)
0117
0118 #define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)
0119
0120
0121 /*
0122  * 21071-CA Control and Status registers.
0123  * These are used to program memory timing,
0124  *  configure memory and initialise the B-Cache.
0125  */
0126 #define APECS_MEM_GCR               (IDENT_ADDR + 0x180000000UL)
0127 #define APECS_MEM_EDSR              (IDENT_ADDR + 0x180000040UL)
0128 #define APECS_MEM_TAR               (IDENT_ADDR + 0x180000060UL)
0129 #define APECS_MEM_ELAR              (IDENT_ADDR + 0x180000080UL)
0130 #define APECS_MEM_EHAR          (IDENT_ADDR + 0x1800000a0UL)
0131 #define APECS_MEM_SFT_RST       (IDENT_ADDR + 0x1800000c0UL)
0132 #define APECS_MEM_LDxLAR        (IDENT_ADDR + 0x1800000e0UL)
0133 #define APECS_MEM_LDxHAR        (IDENT_ADDR + 0x180000100UL)
0134 #define APECS_MEM_GTR           (IDENT_ADDR + 0x180000200UL)
0135 #define APECS_MEM_RTR           (IDENT_ADDR + 0x180000220UL)
0136 #define APECS_MEM_VFPR          (IDENT_ADDR + 0x180000240UL)
0137 #define APECS_MEM_PDLDR         (IDENT_ADDR + 0x180000260UL)
0138 #define APECS_MEM_PDhDR         (IDENT_ADDR + 0x180000280UL)
0139
0140 /* Bank x Base Address Register */
0141 #define APECS_MEM_B0BAR         (IDENT_ADDR + 0x180000800UL)
0142 #define APECS_MEM_B1BAR         (IDENT_ADDR + 0x180000820UL)
0143 #define APECS_MEM_B2BAR         (IDENT_ADDR + 0x180000840UL)
0144 #define APECS_MEM_B3BAR         (IDENT_ADDR + 0x180000860UL)
0145 #define APECS_MEM_B4BAR         (IDENT_ADDR + 0x180000880UL)
0146 #define APECS_MEM_B5BAR         (IDENT_ADDR + 0x1800008A0UL)
0147 #define APECS_MEM_B6BAR         (IDENT_ADDR + 0x1800008C0UL)
0148 #define APECS_MEM_B7BAR         (IDENT_ADDR + 0x1800008E0UL)
0149 #define APECS_MEM_B8BAR         (IDENT_ADDR + 0x180000900UL)
0150
0151 /* Bank x Configuration Register */
0152 #define APECS_MEM_B0BCR         (IDENT_ADDR + 0x180000A00UL)
0153 #define APECS_MEM_B1BCR         (IDENT_ADDR + 0x180000A20UL)
0154 #define APECS_MEM_B2BCR         (IDENT_ADDR + 0x180000A40UL)
0155 #define APECS_MEM_B3BCR         (IDENT_ADDR + 0x180000A60UL)
0156 #define APECS_MEM_B4BCR         (IDENT_ADDR + 0x180000A80UL)
0157 #define APECS_MEM_B5BCR         (IDENT_ADDR + 0x180000AA0UL)
0158 #define APECS_MEM_B6BCR         (IDENT_ADDR + 0x180000AC0UL)
0159 #define APECS_MEM_B7BCR         (IDENT_ADDR + 0x180000AE0UL)
0160 #define APECS_MEM_B8BCR         (IDENT_ADDR + 0x180000B00UL)
0161
0162 /* Bank x Timing Register A */
0163 #define APECS_MEM_B0TRA         (IDENT_ADDR + 0x180000C00UL)
0164 #define APECS_MEM_B1TRA         (IDENT_ADDR + 0x180000C20UL)
0165 #define APECS_MEM_B2TRA         (IDENT_ADDR + 0x180000C40UL)
0166 #define APECS_MEM_B3TRA         (IDENT_ADDR + 0x180000C60UL)
0167 #define APECS_MEM_B4TRA         (IDENT_ADDR + 0x180000C80UL)
0168 #define APECS_MEM_B5TRA         (IDENT_ADDR + 0x180000CA0UL)
0169 #define APECS_MEM_B6TRA         (IDENT_ADDR + 0x180000CC0UL)
0170 #define APECS_MEM_B7TRA         (IDENT_ADDR + 0x180000CE0UL)
0171 #define APECS_MEM_B8TRA         (IDENT_ADDR + 0x180000D00UL)
0172
0173 /* Bank x Timing Register B */
0174 #define APECS_MEM_B0TRB                 (IDENT_ADDR + 0x180000E00UL)
0175 #define APECS_MEM_B1TRB         (IDENT_ADDR + 0x180000E20UL)
0176 #define APECS_MEM_B2TRB         (IDENT_ADDR + 0x180000E40UL)
0177 #define APECS_MEM_B3TRB         (IDENT_ADDR + 0x180000E60UL)
0178 #define APECS_MEM_B4TRB         (IDENT_ADDR + 0x180000E80UL)
0179 #define APECS_MEM_B5TRB         (IDENT_ADDR + 0x180000EA0UL)
0180 #define APECS_MEM_B6TRB         (IDENT_ADDR + 0x180000EC0UL)
0181 #define APECS_MEM_B7TRB         (IDENT_ADDR + 0x180000EE0UL)
0182 #define APECS_MEM_B8TRB         (IDENT_ADDR + 0x180000F00UL)
0183
0184
0185 /*
0186  * Memory spaces:
0187  */
0188 #define APECS_IACK_SC               (IDENT_ADDR + 0x1b0000000UL)
0189 #define APECS_CONF              (IDENT_ADDR + 0x1e0000000UL)
0190 #define APECS_IO            (IDENT_ADDR + 0x1c0000000UL)
0191 #define APECS_SPARSE_MEM        (IDENT_ADDR + 0x200000000UL)
0192 #define APECS_DENSE_MEM             (IDENT_ADDR + 0x300000000UL)
0193
0194
0195 /*
0196  * Bit definitions for I/O Controller status register 0:
0197  */
0198 #define APECS_IOC_STAT0_CMD     0xf
0199 #define APECS_IOC_STAT0_ERR     (1<<4)
0200 #define APECS_IOC_STAT0_LOST        (1<<5)
0201 #define APECS_IOC_STAT0_THIT        (1<<6)
0202 #define APECS_IOC_STAT0_TREF        (1<<7)
0203 #define APECS_IOC_STAT0_CODE_SHIFT  8
0204 #define APECS_IOC_STAT0_CODE_MASK   0x7
0205 #define APECS_IOC_STAT0_P_NBR_SHIFT 13
0206 #define APECS_IOC_STAT0_P_NBR_MASK  0x7ffff
0207
0208 #define APECS_HAE_ADDRESS       APECS_IOC_HAXR1
0209
0210
0211 /*
0212  * Data structure for handling APECS machine checks:
0213  */
0214
0215 struct el_apecs_mikasa_sysdata_mcheck
0216 {
0217     unsigned long coma_gcr;
0218     unsigned long coma_edsr;
0219     unsigned long coma_ter;
0220     unsigned long coma_elar;
0221     unsigned long coma_ehar;
0222     unsigned long coma_ldlr;
0223     unsigned long coma_ldhr;
0224     unsigned long coma_base0;
0225     unsigned long coma_base1;
0226     unsigned long coma_base2;
0227     unsigned long coma_base3;
0228     unsigned long coma_cnfg0;
0229     unsigned long coma_cnfg1;
0230     unsigned long coma_cnfg2;
0231     unsigned long coma_cnfg3;
0232     unsigned long epic_dcsr;
0233     unsigned long epic_pear;
0234     unsigned long epic_sear;
0235     unsigned long epic_tbr1;
0236     unsigned long epic_tbr2;
0237     unsigned long epic_pbr1;
0238     unsigned long epic_pbr2;
0239     unsigned long epic_pmr1;
0240     unsigned long epic_pmr2;
0241     unsigned long epic_harx1;
0242     unsigned long epic_harx2;
0243     unsigned long epic_pmlt;
0244     unsigned long epic_tag0;
0245     unsigned long epic_tag1;
0246     unsigned long epic_tag2;
0247     unsigned long epic_tag3;
0248     unsigned long epic_tag4;
0249     unsigned long epic_tag5;
0250     unsigned long epic_tag6;
0251     unsigned long epic_tag7;
0252     unsigned long epic_data0;
0253     unsigned long epic_data1;
0254     unsigned long epic_data2;
0255     unsigned long epic_data3;
0256     unsigned long epic_data4;
0257     unsigned long epic_data5;
0258     unsigned long epic_data6;
0259     unsigned long epic_data7;
0260
0261     unsigned long pceb_vid;
0262     unsigned long pceb_did;
0263     unsigned long pceb_revision;
0264     unsigned long pceb_command;
0265     unsigned long pceb_status;
0266     unsigned long pceb_latency;
0267     unsigned long pceb_control;
0268     unsigned long pceb_arbcon;
0269     unsigned long pceb_arbpri;
0270
0271     unsigned long esc_id;
0272     unsigned long esc_revision;
0273     unsigned long esc_int0;
0274     unsigned long esc_int1;
0275     unsigned long esc_elcr0;
0276     unsigned long esc_elcr1;
0277     unsigned long esc_last_eisa;
0278     unsigned long esc_nmi_stat;
0279
0280     unsigned long pci_ir;
0281     unsigned long pci_imr;
0282     unsigned long svr_mgr;
0283 };
0284
0285 /* This for the normal APECS machines.  */
0286 struct el_apecs_sysdata_mcheck
0287 {
0288     unsigned long coma_gcr;
0289     unsigned long coma_edsr;
0290     unsigned long coma_ter;
0291     unsigned long coma_elar;
0292     unsigned long coma_ehar;
0293     unsigned long coma_ldlr;
0294     unsigned long coma_ldhr;
0295     unsigned long coma_base0;
0296     unsigned long coma_base1;
0297     unsigned long coma_base2;
0298     unsigned long coma_cnfg0;
0299     unsigned long coma_cnfg1;
0300     unsigned long coma_cnfg2;
0301     unsigned long epic_dcsr;
0302     unsigned long epic_pear;
0303     unsigned long epic_sear;
0304     unsigned long epic_tbr1;
0305     unsigned long epic_tbr2;
0306     unsigned long epic_pbr1;
0307     unsigned long epic_pbr2;
0308     unsigned long epic_pmr1;
0309     unsigned long epic_pmr2;
0310     unsigned long epic_harx1;
0311     unsigned long epic_harx2;
0312     unsigned long epic_pmlt;
0313     unsigned long epic_tag0;
0314     unsigned long epic_tag1;
0315     unsigned long epic_tag2;
0316     unsigned long epic_tag3;
0317     unsigned long epic_tag4;
0318     unsigned long epic_tag5;
0319     unsigned long epic_tag6;
0320     unsigned long epic_tag7;
0321     unsigned long epic_data0;
0322     unsigned long epic_data1;
0323     unsigned long epic_data2;
0324     unsigned long epic_data3;
0325     unsigned long epic_data4;
0326     unsigned long epic_data5;
0327     unsigned long epic_data6;
0328     unsigned long epic_data7;
0329 };
0330
0331 struct el_apecs_procdata
0332 {
0333     unsigned long paltemp[32];  /* PAL TEMP REGS. */
0334     /* EV4-specific fields */
0335     unsigned long exc_addr;     /* Address of excepting instruction. */
0336     unsigned long exc_sum;      /* Summary of arithmetic traps. */
0337     unsigned long exc_mask;     /* Exception mask (from exc_sum). */
0338     unsigned long iccsr;        /* IBox hardware enables. */
0339     unsigned long pal_base;     /* Base address for PALcode. */
0340     unsigned long hier;         /* Hardware Interrupt Enable. */
0341     unsigned long hirr;         /* Hardware Interrupt Request. */
0342     unsigned long csr;          /* D-stream fault info. */
0343     unsigned long dc_stat;      /* D-cache status (ECC/Parity Err). */
0344     unsigned long dc_addr;      /* EV3 Phys Addr for ECC/DPERR. */
0345     unsigned long abox_ctl;     /* ABox Control Register. */
0346     unsigned long biu_stat;     /* BIU Status. */
0347     unsigned long biu_addr;     /* BUI Address. */
0348     unsigned long biu_ctl;      /* BIU Control. */
0349     unsigned long fill_syndrome;/* For correcting ECC errors. */
0350     unsigned long fill_addr;    /* Cache block which was being read */
0351     unsigned long va;           /* Effective VA of fault or miss. */
0352     unsigned long bc_tag;       /* Backup Cache Tag Probe Results.*/
0353 };
0354
0355
0356 #ifdef __KERNEL__
0357
0358 #ifndef __EXTERN_INLINE
0359 #define __EXTERN_INLINE extern inline
0360 #define __IO_EXTERN_INLINE
0361 #endif
0362
0363 /*
0364  * I/O functions:
0365  *
0366  * Unlike Jensen, the APECS machines have no concept of local
0367  * I/O---everything goes over the PCI bus.
0368  *
0369  * There is plenty room for optimization here.  In particular,
0370  * the Alpha's insb/insw/extb/extw should be useful in moving
0371  * data to/from the right byte-lanes.
0372  */
0373
0374 #define vip volatile int __force *
0375 #define vuip    volatile unsigned int __force *
0376 #define vulp    volatile unsigned long __force *
0377
0378 #define APECS_SET_HAE                       \
0379     do {                            \
0380         if (addr >= (1UL << 24)) {          \
0381             unsigned long msb = addr & 0xf8000000;  \
0382             addr -= msb;                \
0383             set_hae(msb);               \
0384         }                       \
0385     } while (0)
0386
0387 __EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr)
0388 {
0389     unsigned long addr = (unsigned long) xaddr;
0390     unsigned long result, base_and_type;
0391
0392     if (addr >= APECS_DENSE_MEM) {
0393         addr -= APECS_DENSE_MEM;
0394         APECS_SET_HAE;
0395         base_and_type = APECS_SPARSE_MEM + 0x00;
0396     } else {
0397         addr -= APECS_IO;
0398         base_and_type = APECS_IO + 0x00;
0399     }
0400
0401     result = *(vip) ((addr << 5) + base_and_type);
0402     return __kernel_extbl(result, addr & 3);
0403 }
0404
0405 __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr)
0406 {
0407     unsigned long addr = (unsigned long) xaddr;
0408     unsigned long w, base_and_type;
0409
0410     if (addr >= APECS_DENSE_MEM) {
0411         addr -= APECS_DENSE_MEM;
0412         APECS_SET_HAE;
0413         base_and_type = APECS_SPARSE_MEM + 0x00;
0414     } else {
0415         addr -= APECS_IO;
0416         base_and_type = APECS_IO + 0x00;
0417     }
0418
0419     w = __kernel_insbl(b, addr & 3);
0420     *(vuip) ((addr << 5) + base_and_type) = w;
0421 }
0422
0423 __EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr)
0424 {
0425     unsigned long addr = (unsigned long) xaddr;
0426     unsigned long result, base_and_type;
0427
0428     if (addr >= APECS_DENSE_MEM) {
0429         addr -= APECS_DENSE_MEM;
0430         APECS_SET_HAE;
0431         base_and_type = APECS_SPARSE_MEM + 0x08;
0432     } else {
0433         addr -= APECS_IO;
0434         base_and_type = APECS_IO + 0x08;
0435     }
0436
0437     result = *(vip) ((addr << 5) + base_and_type);
0438     return __kernel_extwl(result, addr & 3);
0439 }
0440
0441 __EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr)
0442 {
0443     unsigned long addr = (unsigned long) xaddr;
0444     unsigned long w, base_and_type;
0445
0446     if (addr >= APECS_DENSE_MEM) {
0447         addr -= APECS_DENSE_MEM;
0448         APECS_SET_HAE;
0449         base_and_type = APECS_SPARSE_MEM + 0x08;
0450     } else {
0451         addr -= APECS_IO;
0452         base_and_type = APECS_IO + 0x08;
0453     }
0454
0455     w = __kernel_inswl(b, addr & 3);
0456     *(vuip) ((addr << 5) + base_and_type) = w;
0457 }
0458
0459 __EXTERN_INLINE unsigned int apecs_ioread32(const void __iomem *xaddr)
0460 {
0461     unsigned long addr = (unsigned long) xaddr;
0462     if (addr < APECS_DENSE_MEM)
0463         addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
0464     return *(vuip)addr;
0465 }
0466
0467 __EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr)
0468 {
0469     unsigned long addr = (unsigned long) xaddr;
0470     if (addr < APECS_DENSE_MEM)
0471         addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
0472     *(vuip)addr = b;
0473 }
0474
0475 __EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr)
0476 {
0477     return (void __iomem *)(addr + APECS_IO);
0478 }
0479
0480 __EXTERN_INLINE void __iomem *apecs_ioremap(unsigned long addr,
0481                         unsigned long size)
0482 {
0483     return (void __iomem *)(addr + APECS_DENSE_MEM);
0484 }
0485
0486 __EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr)
0487 {
0488     return addr >= IDENT_ADDR + 0x180000000UL;
0489 }
0490
0491 __EXTERN_INLINE int apecs_is_mmio(const volatile void __iomem *addr)
0492 {
0493     return (unsigned long)addr >= APECS_DENSE_MEM;
0494 }
0495
0496 #undef APECS_SET_HAE
0497
0498 #undef vip
0499 #undef vuip
0500 #undef vulp
0501
0502 #undef __IO_PREFIX
0503 #define __IO_PREFIX     apecs
0504 #define apecs_trivial_io_bw 0
0505 #define apecs_trivial_io_lq 0
0506 #define apecs_trivial_rw_bw 2
0507 #define apecs_trivial_rw_lq 1
0508 #define apecs_trivial_iounmap   1
0509 #include <asm/io_trivial.h>
0510
0511 #ifdef __IO_EXTERN_INLINE
0512 #undef __EXTERN_INLINE
0513 #undef __IO_EXTERN_INLINE
0514 #endif
0515
0516 #endif /* __KERNEL__ */
0517
0518 #endif /* __ALPHA_APECS__H__ */