0001 =============================
0002 MMUv3 initialization sequence
0003 =============================
0004
0005 The code in the initialize_mmu macro sets up MMUv3 memory mapping
0006 identically to MMUv2 fixed memory mapping. Depending on
0007 CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
0008 located in addresses it was linked for (symbol undefined), or not
0009 (symbol defined), so it needs to be position-independent.
0010
0011 The code has the following assumptions:
0012
0013 - This code fragment is run only on an MMU v3.
0014 - TLBs are in their reset state.
0015 - ITLBCFG and DTLBCFG are zero (reset state).
0016 - RASID is 0x04030201 (reset state).
0017 - PS.RING is zero (reset state).
0018 - LITBASE is zero (reset state, PC-relative literals); required to be PIC.
0019
0020 TLB setup proceeds along the following steps.
0021
0022 Legend:
0023
0024 - VA = virtual address (two upper nibbles of it);
0025 - PA = physical address (two upper nibbles of it);
0026 - pc = physical range that contains this code;
0027
0028 After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
0029 or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
0030 0x40000000 or above. That address corresponds to next instruction to execute
0031 in this code. After step 4, we jump to intended (linked) address of this code.
0032 The scheme below assumes that the kernel is loaded below 0x40000000.
0033
0034 ====== ===== ===== ===== ===== ====== ===== =====
0035 - Step0 Step1 Step2 Step3 Step4 Step5
0036
0037 VA PA PA PA PA VA PA PA
0038 ====== ===== ===== ===== ===== ====== ===== =====
0039 E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0
0040 C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0
0041 A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00
0042 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00
0043 60..7F -> 60 -> 60 -> 60
0044 40..5F -> 40 -> pc -> pc 40..5F -> pc
0045 20..3F -> 20 -> 20 -> 20
0046 00..1F -> 00 -> 00 -> 00
0047 ====== ===== ===== ===== ===== ====== ===== =====
0048
0049 The default location of IO peripherals is above 0xf0000000. This may be changed
0050 using a "ranges" property in a device tree simple-bus node. See the Devicetree
0051 Specification, section 4.5 for details on the syntax and semantics of
0052 simple-bus nodes. The following limitations apply:
0053
0054 1. Only top level simple-bus nodes are considered
0055
0056 2. Only one (first) simple-bus node is considered
0057
0058 3. Empty "ranges" properties are not supported
0059
0060 4. Only the first triplet in the "ranges" property is considered
0061
0062 5. The parent-bus-address value is rounded down to the nearest 256MB boundary
0063
0064 6. The IO area covers the entire 256MB segment of parent-bus-address; the
0065 "ranges" triplet length field is ignored
0066
0067
0068 MMUv3 address space layouts.
0069 ============================
0070
0071 Default MMUv2-compatible layout::
0072
0073 Symbol VADDR Size
0074 +------------------+
0075 | Userspace | 0x00000000 TASK_SIZE
0076 +------------------+ 0x40000000
0077 +------------------+
0078 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
0079 +------------------+
0080 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
0081 +------------------+ 0x8e400000
0082 +------------------+
0083 | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
0084 +------------------+ VMALLOC_END
0085 +------------------+
0086 | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE
0087 | remap area 1 |
0088 +------------------+
0089 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
0090 | remap area 2 |
0091 +------------------+
0092 +------------------+
0093 | KMAP area | PKMAP_BASE PTRS_PER_PTE *
0094 | | DCACHE_N_COLORS *
0095 | | PAGE_SIZE
0096 | | (4MB * DCACHE_N_COLORS)
0097 +------------------+
0098 | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
0099 | | NR_CPUS *
0100 | | DCACHE_N_COLORS *
0101 | | PAGE_SIZE
0102 +------------------+ FIXADDR_TOP 0xcffff000
0103 +------------------+
0104 | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB
0105 +------------------+
0106 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB
0107 +------------------+
0108 | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
0109 +------------------+
0110 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
0111 +------------------+
0112
0113
0114 256MB cached + 256MB uncached layout::
0115
0116 Symbol VADDR Size
0117 +------------------+
0118 | Userspace | 0x00000000 TASK_SIZE
0119 +------------------+ 0x40000000
0120 +------------------+
0121 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
0122 +------------------+
0123 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
0124 +------------------+ 0x8e400000
0125 +------------------+
0126 | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
0127 +------------------+ VMALLOC_END
0128 +------------------+
0129 | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE
0130 | remap area 1 |
0131 +------------------+
0132 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
0133 | remap area 2 |
0134 +------------------+
0135 +------------------+
0136 | KMAP area | PKMAP_BASE PTRS_PER_PTE *
0137 | | DCACHE_N_COLORS *
0138 | | PAGE_SIZE
0139 | | (4MB * DCACHE_N_COLORS)
0140 +------------------+
0141 | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
0142 | | NR_CPUS *
0143 | | DCACHE_N_COLORS *
0144 | | PAGE_SIZE
0145 +------------------+ FIXADDR_TOP 0xaffff000
0146 +------------------+
0147 | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB
0148 +------------------+
0149 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB
0150 +------------------+
0151 +------------------+
0152 | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
0153 +------------------+
0154 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
0155 +------------------+
0156
0157
0158 512MB cached + 512MB uncached layout::
0159
0160 Symbol VADDR Size
0161 +------------------+
0162 | Userspace | 0x00000000 TASK_SIZE
0163 +------------------+ 0x40000000
0164 +------------------+
0165 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
0166 +------------------+
0167 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
0168 +------------------+ 0x8e400000
0169 +------------------+
0170 | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
0171 +------------------+ VMALLOC_END
0172 +------------------+
0173 | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE
0174 | remap area 1 |
0175 +------------------+
0176 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
0177 | remap area 2 |
0178 +------------------+
0179 +------------------+
0180 | KMAP area | PKMAP_BASE PTRS_PER_PTE *
0181 | | DCACHE_N_COLORS *
0182 | | PAGE_SIZE
0183 | | (4MB * DCACHE_N_COLORS)
0184 +------------------+
0185 | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
0186 | | NR_CPUS *
0187 | | DCACHE_N_COLORS *
0188 | | PAGE_SIZE
0189 +------------------+ FIXADDR_TOP 0x9ffff000
0190 +------------------+
0191 | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB
0192 +------------------+
0193 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB
0194 +------------------+
0195 | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
0196 +------------------+
0197 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
0198 +------------------+
