0001 ===========================================
0002 Atomic Operation Control (ATOMCTL) Register
0003 ===========================================
0004
0005 We Have Atomic Operation Control (ATOMCTL) Register.
0006 This register determines the effect of using a S32C1I instruction
0007 with various combinations of:
0008
0009 1. With and without an Coherent Cache Controller which
0010 can do Atomic Transactions to the memory internally.
0011
0012 2. With and without An Intelligent Memory Controller which
0013 can do Atomic Transactions itself.
0014
0015 The Core comes up with a default value of for the three types of cache ops::
0016
0017 0x28: (WB: Internal, WT: Internal, BY:Exception)
0018
0019 On the FPGA Cards we typically simulate an Intelligent Memory controller
0020 which can implement RCW transactions. For FPGA cards with an External
0021 Memory controller we let it to the atomic operations internally while
0022 doing a Cached (WB) transaction and use the Memory RCW for un-cached
0023 operations.
0024
0025 For systems without an coherent cache controller, non-MX, we always
0026 use the memory controllers RCW, thought non-MX controlers likely
0027 support the Internal Operation.
0028
0029 CUSTOMER-WARNING:
0030 Virtually all customers buy their memory controllers from vendors that
0031 don't support atomic RCW memory transactions and will likely want to
0032 configure this register to not use RCW.
0033
0034 Developers might find using RCW in Bypass mode convenient when testing
0035 with the cache being bypassed; for example studying cache alias problems.
0036
0037 See Section 4.3.12.4 of ISA; Bits::
0038
0039 WB WT BY
0040 5 4 | 3 2 | 1 0
0041
0042 ========= ================== ================== ===============
0043 2 Bit
0044 Field
0045 Values WB - Write Back WT - Write Thru BY - Bypass
0046 ========= ================== ================== ===============
0047 0 Exception Exception Exception
0048 1 RCW Transaction RCW Transaction RCW Transaction
0049 2 Internal Operation Internal Operation Reserved
0050 3 Reserved Reserved Reserved
0051 ========= ================== ================== ===============
