0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 =================
0004 KVM Lock Overview
0005 =================
0006
0007 1. Acquisition Orders
0008 ---------------------
0009
0010 The acquisition orders for mutexes are as follows:
0011
0012 - kvm->lock is taken outside vcpu->mutex
0013
0014 - kvm->lock is taken outside kvm->slots_lock and kvm->irq_lock
0015
0016 - kvm->slots_lock is taken outside kvm->irq_lock, though acquiring
0017 them together is quite rare.
0018
0019 - Unlike kvm->slots_lock, kvm->slots_arch_lock is released before
0020 synchronize_srcu(&kvm->srcu). Therefore kvm->slots_arch_lock
0021 can be taken inside a kvm->srcu read-side critical section,
0022 while kvm->slots_lock cannot.
0023
0024 - kvm->mn_active_invalidate_count ensures that pairs of
0025 invalidate_range_start() and invalidate_range_end() callbacks
0026 use the same memslots array. kvm->slots_lock and kvm->slots_arch_lock
0027 are taken on the waiting side in install_new_memslots, so MMU notifiers
0028 must not take either kvm->slots_lock or kvm->slots_arch_lock.
0029
0030 On x86:
0031
0032 - vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock
0033
0034 - kvm->arch.mmu_lock is an rwlock. kvm->arch.tdp_mmu_pages_lock and
0035 kvm->arch.mmu_unsync_pages_lock are taken inside kvm->arch.mmu_lock, and
0036 cannot be taken without already holding kvm->arch.mmu_lock (typically with
0037 ``read_lock`` for the TDP MMU, thus the need for additional spinlocks).
0038
0039 Everything else is a leaf: no other lock is taken inside the critical
0040 sections.
0041
0042 2. Exception
0043 ------------
0044
0045 Fast page fault:
0046
0047 Fast page fault is the fast path which fixes the guest page fault out of
0048 the mmu-lock on x86. Currently, the page fault can be fast in one of the
0049 following two cases:
0050
0051 1. Access Tracking: The SPTE is not present, but it is marked for access
0052 tracking. That means we need to restore the saved R/X bits. This is
0053 described in more detail later below.
0054
0055 2. Write-Protection: The SPTE is present and the fault is caused by
0056 write-protect. That means we just need to change the W bit of the spte.
0057
0058 What we use to avoid all the race is the Host-writable bit and MMU-writable bit
0059 on the spte:
0060
0061 - Host-writable means the gfn is writable in the host kernel page tables and in
0062 its KVM memslot.
0063 - MMU-writable means the gfn is writable in the guest's mmu and it is not
0064 write-protected by shadow page write-protection.
0065
0066 On fast page fault path, we will use cmpxchg to atomically set the spte W
0067 bit if spte.HOST_WRITEABLE = 1 and spte.WRITE_PROTECT = 1, to restore the saved
0068 R/X bits if for an access-traced spte, or both. This is safe because whenever
0069 changing these bits can be detected by cmpxchg.
0070
0071 But we need carefully check these cases:
0072
0073 1) The mapping from gfn to pfn
0074
0075 The mapping from gfn to pfn may be changed since we can only ensure the pfn
0076 is not changed during cmpxchg. This is a ABA problem, for example, below case
0077 will happen:
0078
0079 +------------------------------------------------------------------------+
0080 | At the beginning:: |
0081 | |
0082 | gpte = gfn1 |
0083 | gfn1 is mapped to pfn1 on host |
0084 | spte is the shadow page table entry corresponding with gpte and |
0085 | spte = pfn1 |
0086 +------------------------------------------------------------------------+
0087 | On fast page fault path: |
0088 +------------------------------------+-----------------------------------+
0089 | CPU 0: | CPU 1: |
0090 +------------------------------------+-----------------------------------+
0091 | :: | |
0092 | | |
0093 | old_spte = *spte; | |
0094 +------------------------------------+-----------------------------------+
0095 | | pfn1 is swapped out:: |
0096 | | |
0097 | | spte = 0; |
0098 | | |
0099 | | pfn1 is re-alloced for gfn2. |
0100 | | |
0101 | | gpte is changed to point to |
0102 | | gfn2 by the guest:: |
0103 | | |
0104 | | spte = pfn1; |
0105 +------------------------------------+-----------------------------------+
0106 | :: |
0107 | |
0108 | if (cmpxchg(spte, old_spte, old_spte+W) |
0109 | mark_page_dirty(vcpu->kvm, gfn1) |
0110 | OOPS!!! |
0111 +------------------------------------------------------------------------+
0112
0113 We dirty-log for gfn1, that means gfn2 is lost in dirty-bitmap.
0114
0115 For direct sp, we can easily avoid it since the spte of direct sp is fixed
0116 to gfn. For indirect sp, we disabled fast page fault for simplicity.
0117
0118 A solution for indirect sp could be to pin the gfn, for example via
0119 kvm_vcpu_gfn_to_pfn_atomic, before the cmpxchg. After the pinning:
0120
0121 - We have held the refcount of pfn that means the pfn can not be freed and
0122 be reused for another gfn.
0123 - The pfn is writable and therefore it cannot be shared between different gfns
0124 by KSM.
0125
0126 Then, we can ensure the dirty bitmaps is correctly set for a gfn.
0127
0128 2) Dirty bit tracking
0129
0130 In the origin code, the spte can be fast updated (non-atomically) if the
0131 spte is read-only and the Accessed bit has already been set since the
0132 Accessed bit and Dirty bit can not be lost.
0133
0134 But it is not true after fast page fault since the spte can be marked
0135 writable between reading spte and updating spte. Like below case:
0136
0137 +------------------------------------------------------------------------+
0138 | At the beginning:: |
0139 | |
0140 | spte.W = 0 |
0141 | spte.Accessed = 1 |
0142 +------------------------------------+-----------------------------------+
0143 | CPU 0: | CPU 1: |
0144 +------------------------------------+-----------------------------------+
0145 | In mmu_spte_clear_track_bits():: | |
0146 | | |
0147 | old_spte = *spte; | |
0148 | | |
0149 | | |
0150 | /* 'if' condition is satisfied. */| |
0151 | if (old_spte.Accessed == 1 && | |
0152 | old_spte.W == 0) | |
0153 | spte = 0ull; | |
0154 +------------------------------------+-----------------------------------+
0155 | | on fast page fault path:: |
0156 | | |
0157 | | spte.W = 1 |
0158 | | |
0159 | | memory write on the spte:: |
0160 | | |
0161 | | spte.Dirty = 1 |
0162 +------------------------------------+-----------------------------------+
0163 | :: | |
0164 | | |
0165 | else | |
0166 | old_spte = xchg(spte, 0ull) | |
0167 | if (old_spte.Accessed == 1) | |
0168 | kvm_set_pfn_accessed(spte.pfn);| |
0169 | if (old_spte.Dirty == 1) | |
0170 | kvm_set_pfn_dirty(spte.pfn); | |
0171 | OOPS!!! | |
0172 +------------------------------------+-----------------------------------+
0173
0174 The Dirty bit is lost in this case.
0175
0176 In order to avoid this kind of issue, we always treat the spte as "volatile"
0177 if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,
0178 the spte is always atomically updated in this case.
0179
0180 3) flush tlbs due to spte updated
0181
0182 If the spte is updated from writable to readonly, we should flush all TLBs,
0183 otherwise rmap_write_protect will find a read-only spte, even though the
0184 writable spte might be cached on a CPU's TLB.
0185
0186 As mentioned before, the spte can be updated to writable out of mmu-lock on
0187 fast page fault path, in order to easily audit the path, we see if TLBs need
0188 be flushed caused by this reason in mmu_spte_update() since this is a common
0189 function to update spte (present -> present).
0190
0191 Since the spte is "volatile" if it can be updated out of mmu-lock, we always
0192 atomically update the spte, the race caused by fast page fault can be avoided,
0193 See the comments in spte_has_volatile_bits() and mmu_spte_update().
0194
0195 Lockless Access Tracking:
0196
0197 This is used for Intel CPUs that are using EPT but do not support the EPT A/D
0198 bits. In this case, PTEs are tagged as A/D disabled (using ignored bits), and
0199 when the KVM MMU notifier is called to track accesses to a page (via
0200 kvm_mmu_notifier_clear_flush_young), it marks the PTE not-present in hardware
0201 by clearing the RWX bits in the PTE and storing the original R & X bits in more
0202 unused/ignored bits. When the VM tries to access the page later on, a fault is
0203 generated and the fast page fault mechanism described above is used to
0204 atomically restore the PTE to a Present state. The W bit is not saved when the
0205 PTE is marked for access tracking and during restoration to the Present state,
0206 the W bit is set depending on whether or not it was a write access. If it
0207 wasn't, then the W bit will remain clear until a write access happens, at which
0208 time it will be set using the Dirty tracking mechanism described above.
0209
0210 3. Reference
0211 ------------
0212
0213 ``kvm_lock``
0214 ^^^^^^^^^^^^
0215
0216 :Type: mutex
0217 :Arch: any
0218 :Protects: - vm_list
0219
0220 ``kvm_count_lock``
0221 ^^^^^^^^^^^^^^^^^^
0222
0223 :Type: raw_spinlock_t
0224 :Arch: any
0225 :Protects: - hardware virtualization enable/disable
0226 :Comment: 'raw' because hardware enabling/disabling must be atomic /wrt
0227 migration.
0228
0229 ``kvm->mn_invalidate_lock``
0230 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
0231
0232 :Type: spinlock_t
0233 :Arch: any
0234 :Protects: mn_active_invalidate_count, mn_memslots_update_rcuwait
0235
0236 ``kvm_arch::tsc_write_lock``
0237 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
0238
0239 :Type: raw_spinlock_t
0240 :Arch: x86
0241 :Protects: - kvm_arch::{last_tsc_write,last_tsc_nsec,last_tsc_offset}
0242 - tsc offset in vmcb
0243 :Comment: 'raw' because updating the tsc offsets must not be preempted.
0244
0245 ``kvm->mmu_lock``
0246 ^^^^^^^^^^^^^^^^^
0247 :Type: spinlock_t or rwlock_t
0248 :Arch: any
0249 :Protects: -shadow page/shadow tlb entry
0250 :Comment: it is a spinlock since it is used in mmu notifier.
0251
0252 ``kvm->srcu``
0253 ^^^^^^^^^^^^^
0254 :Type: srcu lock
0255 :Arch: any
0256 :Protects: - kvm->memslots
0257 - kvm->buses
0258 :Comment: The srcu read lock must be held while accessing memslots (e.g.
0259 when using gfn_to_* functions) and while accessing in-kernel
0260 MMIO/PIO address->device structure mapping (kvm->buses).
0261 The srcu index can be stored in kvm_vcpu->srcu_idx per vcpu
0262 if it is needed by multiple functions.
0263
0264 ``kvm->slots_arch_lock``
0265 ^^^^^^^^^^^^^^^^^^^^^^^^
0266 :Type: mutex
0267 :Arch: any (only needed on x86 though)
0268 :Protects: any arch-specific fields of memslots that have to be modified
0269 in a ``kvm->srcu`` read-side critical section.
0270 :Comment: must be held before reading the pointer to the current memslots,
0271 until after all changes to the memslots are complete
0272
0273 ``wakeup_vcpus_on_cpu_lock``
0274 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
0275 :Type: spinlock_t
0276 :Arch: x86
0277 :Protects: wakeup_vcpus_on_cpu
0278 :Comment: This is a per-CPU lock and it is used for VT-d posted-interrupts.
0279 When VT-d posted-interrupts is supported and the VM has assigned
0280 devices, we put the blocked vCPU on the list blocked_vcpu_on_cpu
0281 protected by blocked_vcpu_on_cpu_lock, when VT-d hardware issues
0282 wakeup notification event since external interrupts from the
0283 assigned devices happens, we will find the vCPU on the list to
0284 wakeup.
