0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 =========================
0004 MPIC interrupt controller
0005 =========================
0006
0007 Device types supported:
0008
0009 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
0010 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
0011
0012 Only one MPIC instance, of any type, may be instantiated. The created
0013 MPIC will act as the system interrupt controller, connecting to each
0014 vcpu's interrupt inputs.
0015
0016 Groups:
0017 KVM_DEV_MPIC_GRP_MISC
0018 Attributes:
0019
0020 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
0021 Base address of the 256 KiB MPIC register space. Must be
0022 naturally aligned. A value of zero disables the mapping.
0023 Reset value is zero.
0024
0025 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
0026 Access an MPIC register, as if the access were made from the guest.
0027 "attr" is the byte offset into the MPIC register space. Accesses
0028 must be 4-byte aligned.
0029
0030 MSIs may be signaled by using this attribute group to write
0031 to the relevant MSIIR.
0032
0033 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
0034 IRQ input line for each standard openpic source. 0 is inactive and 1
0035 is active, regardless of interrupt sense.
0036
0037 For edge-triggered interrupts: Writing 1 is considered an activating
0038 edge, and writing 0 is ignored. Reading returns 1 if a previously
0039 signaled edge has not been acknowledged, and 0 otherwise.
0040
0041 "attr" is the IRQ number. IRQ numbers for standard sources are the
0042 byte offset of the relevant IVPR from EIVPR0, divided by 32.
0043
0044 IRQ Routing:
0045
0046 The MPIC emulation supports IRQ routing. Only a single MPIC device can
0047 be instantiated. Once that device has been created, it's available as
0048 irqchip id 0.
0049
0050 This irqchip 0 has 256 interrupt pins, which expose the interrupts in
0051 the main array of interrupt sources (a.k.a. "SRC" interrupts).
0052
0053 The numbering is the same as the MPIC device tree binding -- based on
0054 the register offset from the beginning of the sources array, without
0055 regard to any subdivisions in chip documentation such as "internal"
0056 or "external" interrupts.
0057
0058 Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.
