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OSCL-LXR

 
 

    


0001 ================
0002 MSR Trace Events
0003 ================
0004 
0005 The x86 kernel supports tracing most MSR (Model Specific Register) accesses.
0006 To see the definition of the MSRs on Intel systems please see the SDM
0007 at https://www.intel.com/sdm (Volume 3)
0008 
0009 Available trace points:
0010 
0011 /sys/kernel/debug/tracing/events/msr/
0012 
0013 Trace MSR reads:
0014 
0015 read_msr
0016 
0017   - msr: MSR number
0018   - val: Value written
0019   - failed: 1 if the access failed, otherwise 0
0020 
0021 
0022 Trace MSR writes:
0023 
0024 write_msr
0025 
0026   - msr: MSR number
0027   - val: Value written
0028   - failed: 1 if the access failed, otherwise 0
0029 
0030 
0031 Trace RDPMC in kernel:
0032 
0033 rdpmc
0034 
0035 The trace data can be post processed with the postprocess/decode_msr.py script::
0036 
0037   cat /sys/kernel/debug/tracing/trace | decode_msr.py /usr/src/linux/include/asm/msr-index.h
0038 
0039 to add symbolic MSR names.
0040