0001 ==============================================
0002 spi_lm70llp : LM70-LLP parport-to-SPI adapter
0003 ==============================================
0004
0005 Supported board/chip:
0006
0007 * National Semiconductor LM70 LLP evaluation board
0008
0009 Datasheet: http://www.national.com/pf/LM/LM70.html
0010
0011 Author:
0012 Kaiwan N Billimoria <kaiwan@designergraphix.com>
0013
0014 Description
0015 -----------
0016 This driver provides glue code connecting a National Semiconductor LM70 LLP
0017 temperature sensor evaluation board to the kernel's SPI core subsystem.
0018
0019 This is a SPI master controller driver. It can be used in conjunction with
0020 (layered under) the LM70 logical driver (a "SPI protocol driver").
0021 In effect, this driver turns the parallel port interface on the eval board
0022 into a SPI bus with a single device, which will be driven by the generic
0023 LM70 driver (drivers/hwmon/lm70.c).
0024
0025
0026 Hardware Interfacing
0027 --------------------
0028 The schematic for this particular board (the LM70EVAL-LLP) is
0029 available (on page 4) here:
0030
0031 http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf
0032
0033 The hardware interfacing on the LM70 LLP eval board is as follows:
0034
0035 ======== == ========= ==========
0036 Parallel LM70 LLP
0037 Port . Direction JP2 Header
0038 ======== == ========= ==========
0039 D0 2 - -
0040 D1 3 --> V+ 5
0041 D2 4 --> V+ 5
0042 D3 5 --> V+ 5
0043 D4 6 --> V+ 5
0044 D5 7 --> nCS 8
0045 D6 8 --> SCLK 3
0046 D7 9 --> SI/O 5
0047 GND 25 - GND 7
0048 Select 13 <-- SI/O 1
0049 ======== == ========= ==========
0050
0051 Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
0052 is connected to both pin D7 (as Master Out) and Select (as Master In)
0053 using an arrangement that lets either the parport or the LM70 pull the
0054 pin low. This can't be shared with true SPI devices, but other 3-wire
0055 devices might share the same SI/SO pin.
0056
0057 The bitbanger routine in this driver (lm70_txrx) is called back from
0058 the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
0059 spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging.
0060 The lm70 driver then inteprets the resulting digital temperature value
0061 and exports it through sysfs.
0062
0063 A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
0064 shows that the SI/O line from the LM70 chip is connected to the base of a
0065 transistor Q1 (and also a pullup, and a zener diode to D7); while the
0066 collector is tied to VCC.
0067
0068 Interpreting this circuit, when the LM70 SI/O line is High (or tristate
0069 and not grounded by the host via D7), the transistor conducts and switches
0070 the collector to zero, which is reflected on pin 13 of the DB25 parport
0071 connector. When SI/O is Low (driven by the LM70 or the host) on the other
0072 hand, the transistor is cut off and the voltage tied to it's collector is
0073 reflected on pin 13 as a High level.
0074
0075 So: the getmiso inline routine in this driver takes this fact into account,
0076 inverting the value read at pin 13.
0077
0078
0079 Thanks to
0080 ---------
0081
0082 - David Brownell for mentoring the SPI-side driver development.
0083 - Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
0084 - Nadir Billimoria for help interpreting the circuit schematic.
