0001 ==============================
0002 PXA2xx SPI on SSP driver HOWTO
0003 ==============================
0004
0005 This a mini HOWTO on the pxa2xx_spi driver. The driver turns a PXA2xx
0006 synchronous serial port into an SPI master controller
0007 (see Documentation/spi/spi-summary.rst). The driver has the following features
0008
0009 - Support for any PXA2xx and compatible SSP.
0010 - SSP PIO and SSP DMA data transfers.
0011 - External and Internal (SSPFRM) chip selects.
0012 - Per slave device (chip) configuration.
0013 - Full suspend, freeze, resume support.
0014
0015 The driver is built around a &struct spi_message FIFO serviced by kernel
0016 thread. The kernel thread, spi_pump_messages(), drives message FIFO and
0017 is responsible for queuing SPI transactions and setting up and launching
0018 the DMA or interrupt driven transfers.
0019
0020 Declaring PXA2xx Master Controllers
0021 -----------------------------------
0022 Typically, for a legacy platform, an SPI master is defined in the
0023 arch/.../mach-*/board-*.c as a "platform device". The master configuration
0024 is passed to the driver via a table found in include/linux/spi/pxa2xx_spi.h::
0025
0026 struct pxa2xx_spi_controller {
0027 u16 num_chipselect;
0028 u8 enable_dma;
0029 ...
0030 };
0031
0032 The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of
0033 slave device (chips) attached to this SPI master.
0034
0035 The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should
0036 be used. This caused the driver to acquire two DMA channels: Rx channel and
0037 Tx channel. The Rx channel has a higher DMA service priority than the Tx channel.
0038 See the "PXA2xx Developer Manual" section "DMA Controller".
0039
0040 For the new platforms the description of the controller and peripheral devices
0041 comes from Device Tree or ACPI.
0042
0043 NSSP MASTER SAMPLE
0044 ------------------
0045 Below is a sample configuration using the PXA255 NSSP for a legacy platform::
0046
0047 static struct resource pxa_spi_nssp_resources[] = {
0048 [0] = {
0049 .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
0050 .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
0051 .flags = IORESOURCE_MEM,
0052 },
0053 [1] = {
0054 .start = IRQ_NSSP, /* NSSP IRQ */
0055 .end = IRQ_NSSP,
0056 .flags = IORESOURCE_IRQ,
0057 },
0058 };
0059
0060 static struct pxa2xx_spi_controller pxa_nssp_master_info = {
0061 .num_chipselect = 1, /* Matches the number of chips attached to NSSP */
0062 .enable_dma = 1, /* Enables NSSP DMA */
0063 };
0064
0065 static struct platform_device pxa_spi_nssp = {
0066 .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
0067 .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
0068 .resource = pxa_spi_nssp_resources,
0069 .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
0070 .dev = {
0071 .platform_data = &pxa_nssp_master_info, /* Passed to driver */
0072 },
0073 };
0074
0075 static struct platform_device *devices[] __initdata = {
0076 &pxa_spi_nssp,
0077 };
0078
0079 static void __init board_init(void)
0080 {
0081 (void)platform_add_device(devices, ARRAY_SIZE(devices));
0082 }
0083
0084 Declaring Slave Devices
0085 -----------------------
0086 Typically, for a legacy platform, each SPI slave (chip) is defined in the
0087 arch/.../mach-*/board-*.c using the "spi_board_info" structure found in
0088 "linux/spi/spi.h". See "Documentation/spi/spi-summary.rst" for additional
0089 information.
0090
0091 Each slave device attached to the PXA must provide slave specific configuration
0092 information via the structure "pxa2xx_spi_chip" found in
0093 "include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver
0094 will uses the configuration whenever the driver communicates with the slave
0095 device. All fields are optional.
0096
0097 ::
0098
0099 struct pxa2xx_spi_chip {
0100 u8 tx_threshold;
0101 u8 rx_threshold;
0102 u8 dma_burst_size;
0103 u32 timeout;
0104 };
0105
0106 The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
0107 used to configure the SSP hardware FIFO. These fields are critical to the
0108 performance of pxa2xx_spi driver and misconfiguration will result in rx
0109 FIFO overruns (especially in PIO mode transfers). Good default values are::
0110
0111 .tx_threshold = 8,
0112 .rx_threshold = 8,
0113
0114 The range is 1 to 16 where zero indicates "use default".
0115
0116 The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
0117 engine and is related the "spi_device.bits_per_word" field. Read and understand
0118 the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
0119 to determine the correct value. An SSP configured for byte-wide transfers would
0120 use a value of 8. The driver will determine a reasonable default if
0121 dma_burst_size == 0.
0122
0123 The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
0124 trailing bytes in the SSP receiver FIFO. The correct value for this field is
0125 dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
0126 slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
0127 timeouts and must busy-wait any trailing bytes.
0128
0129 NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
0130 chipselect is dropped after each spi_transfer. Most devices need chip select
0131 asserted around the complete message. Use SSPFRM as a GPIO (through a descriptor)
0132 to accommodate these chips.
0133
0134
0135 NSSP SLAVE SAMPLE
0136 -----------------
0137 For a legacy platform or in some other cases, the pxa2xx_spi_chip structure
0138 is passed to the pxa2xx_spi driver in the "spi_board_info.controller_data"
0139 field. Below is a sample configuration using the PXA255 NSSP.
0140
0141 ::
0142
0143 static struct pxa2xx_spi_chip cs8415a_chip_info = {
0144 .tx_threshold = 8, /* SSP hardward FIFO threshold */
0145 .rx_threshold = 8, /* SSP hardward FIFO threshold */
0146 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
0147 .timeout = 235, /* See Intel documentation */
0148 };
0149
0150 static struct pxa2xx_spi_chip cs8405a_chip_info = {
0151 .tx_threshold = 8, /* SSP hardward FIFO threshold */
0152 .rx_threshold = 8, /* SSP hardward FIFO threshold */
0153 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
0154 .timeout = 235, /* See Intel documentation */
0155 };
0156
0157 static struct spi_board_info streetracer_spi_board_info[] __initdata = {
0158 {
0159 .modalias = "cs8415a", /* Name of spi_driver for this device */
0160 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
0161 .bus_num = 2, /* Framework bus number */
0162 .chip_select = 0, /* Framework chip select */
0163 .platform_data = NULL; /* No spi_driver specific config */
0164 .controller_data = &cs8415a_chip_info, /* Master chip config */
0165 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
0166 },
0167 {
0168 .modalias = "cs8405a", /* Name of spi_driver for this device */
0169 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
0170 .bus_num = 2, /* Framework bus number */
0171 .chip_select = 1, /* Framework chip select */
0172 .controller_data = &cs8405a_chip_info, /* Master chip config */
0173 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
0174 },
0175 };
0176
0177 static void __init streetracer_init(void)
0178 {
0179 spi_register_board_info(streetracer_spi_board_info,
0180 ARRAY_SIZE(streetracer_spi_board_info));
0181 }
0182
0183
0184 DMA and PIO I/O Support
0185 -----------------------
0186 The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
0187 transfers. The driver defaults to PIO mode and DMA transfers must be enabled
0188 by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure.
0189 For the newer platforms, that are known to support DMA, the driver will enable
0190 it automatically and try it first with a possible fallback to PIO. The DMA
0191 mode supports both coherent and stream based DMA mappings.
0192
0193 The following logic is used to determine the type of I/O to be used on
0194 a per "spi_transfer" basis::
0195
0196 if !enable_dma then
0197 always use PIO transfers
0198
0199 if spi_message.len > 8191 then
0200 print "rate limited" warning
0201 use PIO transfers
0202
0203 if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
0204 use coherent DMA mode
0205
0206 if rx_buf and tx_buf are aligned on 8 byte boundary then
0207 use streaming DMA mode
0208
0209 otherwise
0210 use PIO transfer
0211
0212 THANKS TO
0213 ---------
0214 David Brownell and others for mentoring the development of this driver.
