0001 ==============
0002 Audio Clocking
0003 ==============
0004
0005 This text describes the audio clocking terms in ASoC and digital audio in
0006 general. Note: Audio clocking can be complex!
0007
0008
0009 Master Clock
0010 ------------
0011
0012 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
0013 or SYSCLK). This audio master clock can be derived from a number of sources
0014 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
0015 audio playback and capture sample rates.
0016
0017 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
0018 their speed can be altered by software (depending on the system use and to save
0019 power). Other master clocks are fixed at a set frequency (i.e. crystals).
0020
0021
0022 DAI Clocks
0023 ----------
0024 The Digital Audio Interface is usually driven by a Bit Clock (often referred to
0025 as BCLK). This clock is used to drive the digital audio data across the link
0026 between the codec and CPU.
0027
0028 The DAI also has a frame clock to signal the start of each audio frame. This
0029 clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
0030 runs at exactly the sample rate (LRC = Rate).
0031
0032 Bit Clock can be generated as follows:-
0033
0034 - BCLK = MCLK / x, or
0035 - BCLK = LRC * x, or
0036 - BCLK = LRC * Channels * Word Size
0037
0038 This relationship depends on the codec or SoC CPU in particular. In general
0039 it is best to configure BCLK to the lowest possible speed (depending on your
0040 rate, number of channels and word size) to save on power.
0041
0042 It is also desirable to use the codec (if possible) to drive (or master) the
0043 audio clocks as it usually gives more accurate sample rates than the CPU.
0044
0045
0046
