0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 ==========================================
0004 Notes on register bank usage in the kernel
0005 ==========================================
0006
0007 Introduction
0008 ------------
0009
0010 The SH-3 and SH-4 CPU families traditionally include a single partial register
0011 bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
0012 may have more full-featured banking or simply no such capabilities at all.
0013
0014 SR.RB banking
0015 -------------
0016
0017 In the case of this type of banking, banked registers are mapped directly to
0018 r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
0019 can still be used to reference the banked registers (as r0_bank ... r7_bank)
0020 when in the context of another bank. The developer must keep the SR.RB value
0021 in mind when writing code that utilizes these banked registers, for obvious
0022 reasons. Userspace is also not able to poke at the bank1 values, so these can
0023 be used rather effectively as scratch registers by the kernel.
0024
0025 Presently the kernel uses several of these registers.
0026
0027 - r0_bank, r1_bank (referenced as k0 and k1, used for scratch
0028 registers when doing exception handling).
0029
0030 - r2_bank (used to track the EXPEVT/INTEVT code)
0031
0032 - Used by do_IRQ() and friends for doing irq mapping based off
0033 of the interrupt exception vector jump table offset
0034
0035 - r6_bank (global interrupt mask)
0036
0037 - The SR.IMASK interrupt handler makes use of this to set the
0038 interrupt priority level (used by local_irq_enable())
0039
0040 - r7_bank (current)
