0001 .. SPDX-License-Identifier: GPL-2.0
0002 .. include:: <isonum.txt>
0003
0004 ======================================================
0005 Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop)
0006 ======================================================
0007
0008 Controller Register Map
0009 -----------------------
0010
0011 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
0012
0013 ============== ==================================
0014 BAR0 offset Register
0015 ============== ==================================
0016 0x11C5C Link Interface IRQ Set
0017 0x11C60 Link Interface IRQ Clear
0018 ============== ==================================
0019
0020 ============== ==================================
0021 BAR2 offset Register
0022 ============== ==================================
0023 0x10 Inbound Message Register 0
0024 0x14 Inbound Message Register 1
0025 0x18 Outbound Message Register 0
0026 0x1C Outbound Message Register 1
0027 0x20 Inbound Doorbell Register
0028 0x24 Inbound Interrupt Status Register
0029 0x28 Inbound Interrupt Mask Register
0030 0x30 Outbound Interrupt Status Register
0031 0x34 Outbound Interrupt Mask Register
0032 0x40 Inbound Queue Port
0033 0x44 Outbound Queue Port
0034 ============== ==================================
0035
0036 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
0037
0038 ============== ==================================
0039 BAR0 offset Register
0040 ============== ==================================
0041 0x10 Inbound Message Register 0
0042 0x14 Inbound Message Register 1
0043 0x18 Outbound Message Register 0
0044 0x1C Outbound Message Register 1
0045 0x20 Inbound Doorbell Register
0046 0x24 Inbound Interrupt Status Register
0047 0x28 Inbound Interrupt Mask Register
0048 0x30 Outbound Interrupt Status Register
0049 0x34 Outbound Interrupt Mask Register
0050 0x40 Inbound Queue Port
0051 0x44 Outbound Queue Port
0052 ============== ==================================
0053
0054 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
0055
0056 ============== ==================================
0057 BAR0 offset Register
0058 ============== ==================================
0059 0x20400 Inbound Doorbell Register
0060 0x20404 Inbound Interrupt Mask Register
0061 0x20408 Outbound Doorbell Register
0062 0x2040C Outbound Interrupt Mask Register
0063 ============== ==================================
0064
0065 ============== ==================================
0066 BAR1 offset Register
0067 ============== ==================================
0068 0x0 Inbound Queue Head Pointer
0069 0x4 Inbound Queue Tail Pointer
0070 0x8 Outbound Queue Head Pointer
0071 0xC Outbound Queue Tail Pointer
0072 0x10 Inbound Message Register
0073 0x14 Outbound Message Register
0074 0x40-0x1040 Inbound Queue
0075 0x1040-0x2040 Outbound Queue
0076 ============== ==================================
0077
0078 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
0079
0080 ============== ==================================
0081 BAR0 offset Register
0082 ============== ==================================
0083 0x0 IOP configuration information.
0084 ============== ==================================
0085
0086 ============== ===================================================
0087 BAR1 offset Register
0088 ============== ===================================================
0089 0x4000 Inbound List Base Address Low
0090 0x4004 Inbound List Base Address High
0091 0x4018 Inbound List Write Pointer
0092 0x402C Inbound List Configuration and Control
0093 0x4050 Outbound List Base Address Low
0094 0x4054 Outbound List Base Address High
0095 0x4058 Outbound List Copy Pointer Shadow Base Address Low
0096 0x405C Outbound List Copy Pointer Shadow Base Address High
0097 0x4088 Outbound List Interrupt Cause
0098 0x408C Outbound List Interrupt Enable
0099 0x1020C PCIe Function 0 Interrupt Enable
0100 0x10400 PCIe Function 0 to CPU Message A
0101 0x10420 CPU to PCIe Function 0 Message A
0102 0x10480 CPU to PCIe Function 0 Doorbell
0103 0x10484 CPU to PCIe Function 0 Doorbell Enable
0104 ============== ===================================================
0105
0106
0107 I/O Request Workflow of Not Marvell Frey
0108 ----------------------------------------
0109
0110 All queued requests are handled via inbound/outbound queue port.
0111 A request packet can be allocated in either IOP or host memory.
0112
0113 To send a request to the controller:
0114
0115 - Get a free request packet by reading the inbound queue port or
0116 allocate a free request in host DMA coherent memory.
0117
0118 The value returned from the inbound queue port is an offset
0119 relative to the IOP BAR0.
0120
0121 Requests allocated in host memory must be aligned on 32-bytes boundary.
0122
0123 - Fill the packet.
0124
0125 - Post the packet to IOP by writing it to inbound queue. For requests
0126 allocated in IOP memory, write the offset to inbound queue port. For
0127 requests allocated in host memory, write (0x80000000|(bus_addr>>5))
0128 to the inbound queue port.
0129
0130 - The IOP process the request. When the request is completed, it
0131 will be put into outbound queue. An outbound interrupt will be
0132 generated.
0133
0134 For requests allocated in IOP memory, the request offset is posted to
0135 outbound queue.
0136
0137 For requests allocated in host memory, (0x80000000|(bus_addr>>5))
0138 is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT
0139 flag is set in the request, the low 32-bit context value will be
0140 posted instead.
0141
0142 - The host read the outbound queue and complete the request.
0143
0144 For requests allocated in IOP memory, the host driver free the request
0145 by writing it to the outbound queue.
0146
0147 Non-queued requests (reset/flush etc) can be sent via inbound message
0148 register 0. An outbound message with the same value indicates the completion
0149 of an inbound message.
0150
0151
0152 I/O Request Workflow of Marvell Frey
0153 ------------------------------------
0154
0155 All queued requests are handled via inbound/outbound list.
0156
0157 To send a request to the controller:
0158
0159 - Allocate a free request in host DMA coherent memory.
0160
0161 Requests allocated in host memory must be aligned on 32-bytes boundary.
0162
0163 - Fill the request with index of the request in the flag.
0164
0165 Fill a free inbound list unit with the physical address and the size of
0166 the request.
0167
0168 Set up the inbound list write pointer with the index of previous unit,
0169 round to 0 if the index reaches the supported count of requests.
0170
0171 - Post the inbound list writer pointer to IOP.
0172
0173 - The IOP process the request. When the request is completed, the flag of
0174 the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a
0175 free outbound list unit and the index of the outbound list unit will be
0176 put into the copy pointer shadow register. An outbound interrupt will be
0177 generated.
0178
0179 - The host read the outbound list copy pointer shadow register and compare
0180 with previous saved read pointer N. If they are different, the host will
0181 read the (N+1)th outbound list unit.
0182
0183 The host get the index of the request from the (N+1)th outbound list
0184 unit and complete the request.
0185
0186 Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe
0187 Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register
0188 with the same value indicates the completion of message.
0189
0190
0191 User-level Interface
0192 ---------------------
0193
0194 The driver exposes following sysfs attributes:
0195
0196 ================== === ========================
0197 NAME R/W Description
0198 ================== === ========================
0199 driver-version R driver version string
0200 firmware-version R firmware version string
0201 ================== === ========================
0202
0203
0204 -----------------------------------------------------------------------------
0205
0206 Copyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.
0207
0208 This file is distributed in the hope that it will be useful,
0209 but WITHOUT ANY WARRANTY; without even the implied warranty of
0210 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0211 GNU General Public License for more details.
0212
0213 linux@highpoint-tech.com
0214
0215 http://www.highpoint-tech.com
