0001 .. _elf_hwcaps_powerpc:
0002
0003 ==================
0004 POWERPC ELF HWCAPs
0005 ==================
0006
0007 This document describes the usage and semantics of the powerpc ELF HWCAPs.
0008
0009
0010 1. Introduction
0011 ---------------
0012
0013 Some hardware or software features are only available on some CPU
0014 implementations, and/or with certain kernel configurations, but have no other
0015 discovery mechanism available to userspace code. The kernel exposes the
0016 presence of these features to userspace through a set of flags called HWCAPs,
0017 exposed in the auxiliary vector.
0018
0019 Userspace software can test for features by acquiring the AT_HWCAP or
0020 AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
0021 flags are set, e.g.::
0022
0023 bool floating_point_is_present(void)
0024 {
0025 unsigned long HWCAPs = getauxval(AT_HWCAP);
0026 if (HWCAPs & PPC_FEATURE_HAS_FPU)
0027 return true;
0028
0029 return false;
0030 }
0031
0032 Where software relies on a feature described by a HWCAP, it should check the
0033 relevant HWCAP flag to verify that the feature is present before attempting to
0034 make use of the feature.
0035
0036 HWCAP is the preferred method to test for the presence of a feature rather
0037 than probing through other means, which may not be reliable or may cause
0038 unpredictable behaviour.
0039
0040 Software that targets a particular platform does not necessarily have to
0041 test for required or implied features. For example if the program requires
0042 FPU, VMX, VSX, it is not necessary to test those HWCAPs, and it may be
0043 impossible to do so if the compiler generates code requiring those features.
0044
0045 2. Facilities
0046 -------------
0047
0048 The Power ISA uses the term "facility" to describe a class of instructions,
0049 registers, interrupts, etc. The presence or absence of a facility indicates
0050 whether this class is available to be used, but the specifics depend on the
0051 ISA version. For example, if the VSX facility is available, the VSX
0052 instructions that can be used differ between the v3.0B and v3.1B ISA
0053 versions.
0054
0055 3. Categories
0056 -------------
0057
0058 The Power ISA before v3.0 uses the term "category" to describe certain
0059 classes of instructions and operating modes which may be optional or
0060 mutually exclusive, the exact meaning of the HWCAP flag may depend on
0061 context, e.g., the presence of the BOOKE feature implies that the server
0062 category is not implemented.
0063
0064 4. HWCAP allocation
0065 -------------------
0066
0067 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
0068 Specification (which will be reflected in the kernel's uapi headers).
0069
0070 5. The HWCAPs exposed in AT_HWCAP
0071 ---------------------------------
0072
0073 PPC_FEATURE_32
0074 32-bit CPU
0075
0076 PPC_FEATURE_64
0077 64-bit CPU (userspace may be running in 32-bit mode).
0078
0079 PPC_FEATURE_601_INSTR
0080 The processor is PowerPC 601.
0081 Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")
0082
0083 PPC_FEATURE_HAS_ALTIVEC
0084 Vector (aka Altivec, VMX) facility is available.
0085
0086 PPC_FEATURE_HAS_FPU
0087 Floating point facility is available.
0088
0089 PPC_FEATURE_HAS_MMU
0090 Memory management unit is present and enabled.
0091
0092 PPC_FEATURE_HAS_4xxMAC
0093 The processor is 40x or 44x family.
0094
0095 PPC_FEATURE_UNIFIED_CACHE
0096 The processor has a unified L1 cache for instructions and data, as
0097 found in NXP e200.
0098 Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
0099
0100 PPC_FEATURE_HAS_SPE
0101 Signal Processing Engine facility is available.
0102
0103 PPC_FEATURE_HAS_EFP_SINGLE
0104 Embedded Floating Point single precision operations are available.
0105
0106 PPC_FEATURE_HAS_EFP_DOUBLE
0107 Embedded Floating Point double precision operations are available.
0108
0109 PPC_FEATURE_NO_TB
0110 The timebase facility (mftb instruction) is not available.
0111 This is a 601 specific HWCAP, so if it is known that the processor
0112 running is not a 601, via other HWCAPs or other means, it is not
0113 required to test this bit before using the timebase.
0114 Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")
0115
0116 PPC_FEATURE_POWER4
0117 The processor is POWER4 or PPC970/FX/MP.
0118 POWER4 support dropped from the kernel since 471d7ff8b51b ("powerpc/64s: Remove POWER4 support")
0119
0120 PPC_FEATURE_POWER5
0121 The processor is POWER5.
0122
0123 PPC_FEATURE_POWER5_PLUS
0124 The processor is POWER5+.
0125
0126 PPC_FEATURE_CELL
0127 The processor is Cell.
0128
0129 PPC_FEATURE_BOOKE
0130 The processor implements the embedded category ("BookE") architecture.
0131
0132 PPC_FEATURE_SMT
0133 The processor implements SMT.
0134
0135 PPC_FEATURE_ICACHE_SNOOP
0136 The processor icache is coherent with the dcache, and instruction storage
0137 can be made consistent with data storage for the purpose of executing
0138 instructions with the sequence (as described in, e.g., POWER9 Processor
0139 User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi))::
0140
0141 sync
0142 icbi (to any address)
0143 isync
0144
0145 PPC_FEATURE_ARCH_2_05
0146 The processor supports the v2.05 userlevel architecture. Processors
0147 supporting later architectures DO NOT set this feature.
0148
0149 PPC_FEATURE_PA6T
0150 The processor is PA6T.
0151
0152 PPC_FEATURE_HAS_DFP
0153 DFP facility is available.
0154
0155 PPC_FEATURE_POWER6_EXT
0156 The processor is POWER6.
0157
0158 PPC_FEATURE_ARCH_2_06
0159 The processor supports the v2.06 userlevel architecture. Processors
0160 supporting later architectures also set this feature.
0161
0162 PPC_FEATURE_HAS_VSX
0163 VSX facility is available.
0164
0165 PPC_FEATURE_PSERIES_PERFMON_COMPAT
0166 The processor supports architected PMU events in the range 0xE0-0xFF.
0167
0168 PPC_FEATURE_TRUE_LE
0169 The processor supports true little-endian mode.
0170
0171 PPC_FEATURE_PPC_LE
0172 The processor supports "PowerPC Little-Endian", that uses address
0173 munging to make storage access appear to be little-endian, but the
0174 data is stored in a different format that is unsuitable to be
0175 accessed by other agents not running in this mode.
0176
0177 6. The HWCAPs exposed in AT_HWCAP2
0178 ----------------------------------
0179
0180 PPC_FEATURE2_ARCH_2_07
0181 The processor supports the v2.07 userlevel architecture. Processors
0182 supporting later architectures also set this feature.
0183
0184 PPC_FEATURE2_HTM
0185 Transactional Memory feature is available.
0186
0187 PPC_FEATURE2_DSCR
0188 DSCR facility is available.
0189
0190 PPC_FEATURE2_EBB
0191 EBB facility is available.
0192
0193 PPC_FEATURE2_ISEL
0194 isel instruction is available. This is superseded by ARCH_2_07 and
0195 later.
0196
0197 PPC_FEATURE2_TAR
0198 TAR facility is available.
0199
0200 PPC_FEATURE2_VEC_CRYPTO
0201 v2.07 crypto instructions are available.
0202
0203 PPC_FEATURE2_HTM_NOSC
0204 System calls fail if called in a transactional state, see
0205 Documentation/powerpc/syscall64-abi.rst
0206
0207 PPC_FEATURE2_ARCH_3_00
0208 The processor supports the v3.0B / v3.0C userlevel architecture. Processors
0209 supporting later architectures also set this feature.
0210
0211 PPC_FEATURE2_HAS_IEEE128
0212 IEEE 128-bit binary floating point is supported with VSX
0213 quad-precision instructions and data types.
0214
0215 PPC_FEATURE2_DARN
0216 darn instruction is available.
0217
0218 PPC_FEATURE2_SCV
0219 The scv 0 instruction may be used for system calls, see
0220 Documentation/powerpc/syscall64-abi.rst.
0221
0222 PPC_FEATURE2_HTM_NO_SUSPEND
0223 A limited Transactional Memory facility that does not support suspend is
0224 available, see Documentation/powerpc/transactional_memory.rst.
0225
0226 PPC_FEATURE2_ARCH_3_1
0227 The processor supports the v3.1 userlevel architecture. Processors
0228 supporting later architectures also set this feature.
0229
0230 PPC_FEATURE2_MMA
0231 MMA facility is available.
