0001 ===================================
0002 DSCR (Data Stream Control Register)
0003 ===================================
0004
0005 DSCR register in powerpc allows user to have some control of prefetch of data
0006 stream in the processor. Please refer to the ISA documents or related manual
0007 for more detailed information regarding how to use this DSCR to attain this
0008 control of the prefetches . This document here provides an overview of kernel
0009 support for DSCR, related kernel objects, it's functionalities and exported
0010 user interface.
0011
0012 (A) Data Structures:
0013
0014 (1) thread_struct::
0015
0016 dscr /* Thread DSCR value */
0017 dscr_inherit /* Thread has changed default DSCR */
0018
0019 (2) PACA::
0020
0021 dscr_default /* per-CPU DSCR default value */
0022
0023 (3) sysfs.c::
0024
0025 dscr_default /* System DSCR default value */
0026
0027 (B) Scheduler Changes:
0028
0029 Scheduler will write the per-CPU DSCR default which is stored in the
0030 CPU's PACA value into the register if the thread has dscr_inherit value
0031 cleared which means that it has not changed the default DSCR till now.
0032 If the dscr_inherit value is set which means that it has changed the
0033 default DSCR value, scheduler will write the changed value which will
0034 now be contained in thread struct's dscr into the register instead of
0035 the per-CPU default PACA based DSCR value.
0036
0037 NOTE: Please note here that the system wide global DSCR value never
0038 gets used directly in the scheduler process context switch at all.
0039
0040 (C) SYSFS Interface:
0041
0042 - Global DSCR default: /sys/devices/system/cpu/dscr_default
0043 - CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr
0044
0045 Changing the global DSCR default in the sysfs will change all the CPU
0046 specific DSCR defaults immediately in their PACA structures. Again if
0047 the current process has the dscr_inherit clear, it also writes the new
0048 value into every CPU's DSCR register right away and updates the current
0049 thread's DSCR value as well.
0050
0051 Changing the CPU specific DSCR default value in the sysfs does exactly
0052 the same thing as above but unlike the global one above, it just changes
0053 stuff for that particular CPU instead for all the CPUs on the system.
0054
0055 (D) User Space Instructions:
0056
0057 The DSCR register can be accessed in the user space using any of these
0058 two SPR numbers available for that purpose.
0059
0060 (1) Problem state SPR: 0x03 (Un-privileged, POWER8 only)
0061 (2) Privileged state SPR: 0x11 (Privileged)
0062
0063 Accessing DSCR through privileged SPR number (0x11) from user space
0064 works, as it is emulated following an illegal instruction exception
0065 inside the kernel. Both mfspr and mtspr instructions are emulated.
0066
0067 Accessing DSCR through user level SPR (0x03) from user space will first
0068 create a facility unavailable exception. Inside this exception handler
0069 all mfspr instruction based read attempts will get emulated and returned
0070 where as the first mtspr instruction based write attempts will enable
0071 the DSCR facility for the next time around (both for read and write) by
0072 setting DSCR facility in the FSCR register.
0073
0074 (E) Specifics about 'dscr_inherit':
0075
0076 The thread struct element 'dscr_inherit' represents whether the thread
0077 in question has attempted and changed the DSCR itself using any of the
0078 following methods. This element signifies whether the thread wants to
0079 use the CPU default DSCR value or its own changed DSCR value in the
0080 kernel.
0081
0082 (1) mtspr instruction (SPR number 0x03)
0083 (2) mtspr instruction (SPR number 0x11)
0084 (3) ptrace interface (Explicitly set user DSCR value)
0085
0086 Any child of the process created after this event in the process inherits
0087 this same behaviour as well.
