0001 ==============
0002 OpenRISC Linux
0003 ==============
0004
0005 This is a port of Linux to the OpenRISC class of microprocessors; the initial
0006 target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
0007
0008 For information about OpenRISC processors and ongoing development:
0009
0010 ======= =============================
0011 website https://openrisc.io
0012 email openrisc@lists.librecores.org
0013 ======= =============================
0014
0015 ---------------------------------------------------------------------
0016
0017 Build instructions for OpenRISC toolchain and Linux
0018 ===================================================
0019
0020 In order to build and run Linux for OpenRISC, you'll need at least a basic
0021 toolchain and, perhaps, the architectural simulator. Steps to get these bits
0022 in place are outlined here.
0023
0024 1) Toolchain
0025
0026 Toolchain binaries can be obtained from openrisc.io or our github releases page.
0027 Instructions for building the different toolchains can be found on openrisc.io
0028 or Stafford's toolchain build and release scripts.
0029
0030 ========== =================================================
0031 binaries https://github.com/openrisc/or1k-gcc/releases
0032 toolchains https://openrisc.io/software
0033 building https://github.com/stffrdhrn/or1k-toolchain-build
0034 ========== =================================================
0035
0036 2) Building
0037
0038 Build the Linux kernel as usual::
0039
0040 make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig
0041 make ARCH=openrisc CROSS_COMPILE="or1k-linux-"
0042
0043 3) Running on FPGA (optional)
0044
0045 The OpenRISC community typically uses FuseSoC to manage building and programming
0046 an SoC into an FPGA. The below is an example of programming a De0 Nano
0047 development board with the OpenRISC SoC. During the build FPGA RTL is code
0048 downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
0049 tools. Binaries are loaded onto the board with openocd.
0050
0051 ::
0052
0053 git clone https://github.com/olofk/fusesoc
0054 cd fusesoc
0055 sudo pip install -e .
0056
0057 fusesoc init
0058 fusesoc build de0_nano
0059 fusesoc pgm de0_nano
0060
0061 openocd -f interface/altera-usb-blaster.cfg \
0062 -f board/or1k_generic.cfg
0063
0064 telnet localhost 4444
0065 > init
0066 > halt; load_image vmlinux ; reset
0067
0068 4) Running on a Simulator (optional)
0069
0070 QEMU is a processor emulator which we recommend for simulating the OpenRISC
0071 platform. Please follow the OpenRISC instructions on the QEMU website to get
0072 Linux running on QEMU. You can build QEMU yourself, but your Linux distribution
0073 likely provides binary packages to support OpenRISC.
0074
0075 ============= ======================================================
0076 qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC
0077 ============= ======================================================
0078
0079 ---------------------------------------------------------------------
0080
0081 Terminology
0082 ===========
0083
0084 In the code, the following particles are used on symbols to limit the scope
0085 to more or less specific processor implementations:
0086
0087 ========= =======================================
0088 openrisc: the OpenRISC class of processors
0089 or1k: the OpenRISC 1000 family of processors
0090 or1200: the OpenRISC 1200 processor
0091 ========= =======================================
0092
0093 ---------------------------------------------------------------------
0094
0095 History
0096 ========
0097
0098 18-11-2003 Matjaz Breskvar (phoenix@bsemi.com)
0099 initial port of linux to OpenRISC/or32 architecture.
0100 all the core stuff is implemented and seams usable.
0101
0102 08-12-2003 Matjaz Breskvar (phoenix@bsemi.com)
0103 complete change of TLB miss handling.
0104 rewrite of exceptions handling.
0105 fully functional sash-3.6 in default initrd.
0106 a much improved version with changes all around.
0107
0108 10-04-2004 Matjaz Breskvar (phoenix@bsemi.com)
0109 alot of bugfixes all over.
0110 ethernet support, functional http and telnet servers.
0111 running many standard linux apps.
0112
0113 26-06-2004 Matjaz Breskvar (phoenix@bsemi.com)
0114 port to 2.6.x
0115
0116 30-11-2004 Matjaz Breskvar (phoenix@bsemi.com)
0117 lots of bugfixes and enhancments.
0118 added opencores framebuffer driver.
0119
0120 09-10-2010 Jonas Bonn (jonas@southpole.se)
0121 major rewrite to bring up to par with upstream Linux 2.6.36
