0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 ========================
0004 Spear PCIe Gadget Driver
0005 ========================
0006
0007 Author
0008 ======
0009 Pratyush Anand (pratyush.anand@gmail.com)
0010
0011 Location
0012 ========
0013 driver/misc/spear13xx_pcie_gadget.c
0014
0015 Supported Chip:
0016 ===============
0017 SPEAr1300
0018 SPEAr1310
0019
0020 Menuconfig option:
0021 ==================
0022 Device Drivers
0023 Misc devices
0024 PCIe gadget support for SPEAr13XX platform
0025
0026 purpose
0027 =======
0028 This driver has several nodes which can be read/written by configfs interface.
0029 Its main purpose is to configure selected dual mode PCIe controller as device
0030 and then program its various registers to configure it as a particular device
0031 type. This driver can be used to show spear's PCIe device capability.
0032
0033 Description of different nodes:
0034 ===============================
0035
0036 read behavior of nodes:
0037 -----------------------
0038
0039 =============== ==============================================================
0040 link gives ltssm status.
0041 int_type type of supported interrupt
0042 no_of_msi zero if MSI is not enabled by host. A positive value is the
0043 number of MSI vector granted.
0044 vendor_id returns programmed vendor id (hex)
0045 device_id returns programmed device id(hex)
0046 bar0_size: returns size of bar0 in hex.
0047 bar0_address returns address of bar0 mapped area in hex.
0048 bar0_rw_offset returns offset of bar0 for which bar0_data will return value.
0049 bar0_data returns data at bar0_rw_offset.
0050 =============== ==============================================================
0051
0052 write behavior of nodes:
0053 ------------------------
0054
0055 =============== ================================================================
0056 link write UP to enable ltsmm DOWN to disable
0057 int_type write interrupt type to be configured and (int_type could be
0058 INTA, MSI or NO_INT). Select MSI only when you have programmed
0059 no_of_msi node.
0060 no_of_msi number of MSI vector needed.
0061 inta write 1 to assert INTA and 0 to de-assert.
0062 send_msi write MSI vector to be sent.
0063 vendor_id write vendor id(hex) to be programmed.
0064 device_id write device id(hex) to be programmed.
0065 bar0_size write size of bar0 in hex. default bar0 size is 1000 (hex)
0066 bytes.
0067 bar0_address write address of bar0 mapped area in hex. (default mapping of
0068 bar0 is SYSRAM1(E0800000). Always program bar size before bar
0069 address. Kernel might modify bar size and address for alignment,
0070 so read back bar size and address after writing to cross check.
0071 bar0_rw_offset write offset of bar0 for which bar0_data will write value.
0072 bar0_data write data to be written at bar0_rw_offset.
0073 =============== ================================================================
0074
0075 Node programming example
0076 ========================
0077
0078 Program all PCIe registers in such a way that when this device is connected
0079 to the PCIe host, then host sees this device as 1MB RAM.
0080
0081 ::
0082
0083 #mount -t configfs none /Config
0084
0085 For nth PCIe Device Controller::
0086
0087 # cd /config/pcie_gadget.n/
0088
0089 Now you have all the nodes in this directory.
0090 program vendor id as 0x104a::
0091
0092 # echo 104A >> vendor_id
0093
0094 program device id as 0xCD80::
0095
0096 # echo CD80 >> device_id
0097
0098 program BAR0 size as 1MB::
0099
0100 # echo 100000 >> bar0_size
0101
0102 check for programmed bar0 size::
0103
0104 # cat bar0_size
0105
0106 Program BAR0 Address as DDR (0x2100000). This is the physical address of
0107 memory, which is to be made visible to PCIe host. Similarly any other peripheral
0108 can also be made visible to PCIe host. E.g., if you program base address of UART
0109 as BAR0 address then when this device will be connected to a host, it will be
0110 visible as UART.
0111
0112 ::
0113
0114 # echo 2100000 >> bar0_address
0115
0116 program interrupt type : INTA::
0117
0118 # echo INTA >> int_type
0119
0120 go for link up now::
0121
0122 # echo UP >> link
0123
0124 It will have to be insured that, once link up is done on gadget, then only host
0125 is initialized and start to search PCIe devices on its port.
0126
0127 ::
0128
0129 /*wait till link is up*/
0130 # cat link
0131
0132 Wait till it returns UP.
0133
0134 To assert INTA::
0135
0136 # echo 1 >> inta
0137
0138 To de-assert INTA::
0139
0140 # echo 0 >> inta
0141
0142 if MSI is to be used as interrupt, program no of msi vector needed (say4)::
0143
0144 # echo 4 >> no_of_msi
0145
0146 select MSI as interrupt type::
0147
0148 # echo MSI >> int_type
0149
0150 go for link up now::
0151
0152 # echo UP >> link
0153
0154 wait till link is up::
0155
0156 # cat link
0157
0158 An application can repetitively read this node till link is found UP. It can
0159 sleep between two read.
0160
0161 wait till msi is enabled::
0162
0163 # cat no_of_msi
0164
0165 Should return 4 (number of requested MSI vector)
0166
0167 to send msi vector 2::
0168
0169 # echo 2 >> send_msi
0170 # cd -
