0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 ===============================================
0004 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
0005 ===============================================
0006
0007 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
0008 hardware block. It features up to eight channels, that can be used as
0009 counters, timers, or PWM.
0010
0011 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
0012 have eight channels.
0013
0014 - JZ4725B introduced a separate channel, called Operating System Timer
0015 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
0016 64-bit.
0017
0018 - Each one of the TCU channels has its own clock, which can be reparented to three
0019 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
0020
0021 - The watchdog and OST hardware blocks also feature a TCSR register with the same
0022 format in their register space.
0023 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
0024 OST clocks.
0025
0026 - Each TCU channel works in one of two modes:
0027
0028 - mode TCU1: channels cannot work in sleep mode, but are easier to
0029 operate.
0030 - mode TCU2: channels can work in sleep mode, but the operation is a bit
0031 more complicated than with TCU1 channels.
0032
0033 - The mode of each TCU channel depends on the SoC used:
0034
0035 - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
0036 TCU1 mode.
0037 - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
0038 - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
0039 others operate as TCU1.
0040
0041 - Each channel can generate an interrupt. Some channels share an interrupt
0042 line, some don't, and this changes between SoC versions:
0043
0044 - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
0045 own interrupt line; channels 2-7 share the last interrupt line.
0046 - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
0047 interrupt line; the OST uses the last interrupt line.
0048 - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
0049 channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
0050 the OST uses the last interrupt line.
0051
0052 Implementation
0053 ==============
0054
0055 The functionalities of the TCU hardware are spread across multiple drivers:
0056
0057 =========== =====
0058 clocks drivers/clk/ingenic/tcu.c
0059 interrupts drivers/irqchip/irq-ingenic-tcu.c
0060 timers drivers/clocksource/ingenic-timer.c
0061 OST drivers/clocksource/ingenic-ost.c
0062 PWM drivers/pwm/pwm-jz4740.c
0063 watchdog drivers/watchdog/jz4740_wdt.c
0064 =========== =====
0065
0066 Because various functionalities of the TCU that belong to different drivers
0067 and frameworks can be controlled from the same registers, all of these
0068 drivers access their registers through the same regmap.
0069
0070 For more information regarding the devicetree bindings of the TCU drivers,
0071 have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.
