0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 =======================================
0004 IRQ chip model (hierarchy) of LoongArch
0005 =======================================
0006
0007 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
0008 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
0009 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
0010 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
0011 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
0012 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
0013
0014 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
0015 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
0016 in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
0017 and there are two models of hierarchy (legacy model and extended model).
0018
0019 Legacy IRQ model
0020 ================
0021
0022 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
0023 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
0024 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
0025 to LIOINTC, and then CPUINTC::
0026
0027 +-----+ +---------+ +-------+
0028 | IPI | --> | CPUINTC | <-- | Timer |
0029 +-----+ +---------+ +-------+
0030 ^
0031 |
0032 +---------+ +-------+
0033 | LIOINTC | <-- | UARTs |
0034 +---------+ +-------+
0035 ^
0036 |
0037 +-----------+
0038 | HTVECINTC |
0039 +-----------+
0040 ^ ^
0041 | |
0042 +---------+ +---------+
0043 | PCH-PIC | | PCH-MSI |
0044 +---------+ +---------+
0045 ^ ^ ^
0046 | | |
0047 +---------+ +---------+ +---------+
0048 | PCH-LPC | | Devices | | Devices |
0049 +---------+ +---------+ +---------+
0050 ^
0051 |
0052 +---------+
0053 | Devices |
0054 +---------+
0055
0056 Extended IRQ model
0057 ==================
0058
0059 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
0060 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
0061 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
0062 to CPUINTC directly::
0063
0064 +-----+ +---------+ +-------+
0065 | IPI | --> | CPUINTC | <-- | Timer |
0066 +-----+ +---------+ +-------+
0067 ^ ^
0068 | |
0069 +---------+ +---------+ +-------+
0070 | EIOINTC | | LIOINTC | <-- | UARTs |
0071 +---------+ +---------+ +-------+
0072 ^ ^
0073 | |
0074 +---------+ +---------+
0075 | PCH-PIC | | PCH-MSI |
0076 +---------+ +---------+
0077 ^ ^ ^
0078 | | |
0079 +---------+ +---------+ +---------+
0080 | PCH-LPC | | Devices | | Devices |
0081 +---------+ +---------+ +---------+
0082 ^
0083 |
0084 +---------+
0085 | Devices |
0086 +---------+
0087
0088 ACPI-related definitions
0089 ========================
0090
0091 CPUINTC::
0092
0093 ACPI_MADT_TYPE_CORE_PIC;
0094 struct acpi_madt_core_pic;
0095 enum acpi_madt_core_pic_version;
0096
0097 LIOINTC::
0098
0099 ACPI_MADT_TYPE_LIO_PIC;
0100 struct acpi_madt_lio_pic;
0101 enum acpi_madt_lio_pic_version;
0102
0103 EIOINTC::
0104
0105 ACPI_MADT_TYPE_EIO_PIC;
0106 struct acpi_madt_eio_pic;
0107 enum acpi_madt_eio_pic_version;
0108
0109 HTVECINTC::
0110
0111 ACPI_MADT_TYPE_HT_PIC;
0112 struct acpi_madt_ht_pic;
0113 enum acpi_madt_ht_pic_version;
0114
0115 PCH-PIC::
0116
0117 ACPI_MADT_TYPE_BIO_PIC;
0118 struct acpi_madt_bio_pic;
0119 enum acpi_madt_bio_pic_version;
0120
0121 PCH-MSI::
0122
0123 ACPI_MADT_TYPE_MSI_PIC;
0124 struct acpi_madt_msi_pic;
0125 enum acpi_madt_msi_pic_version;
0126
0127 PCH-LPC::
0128
0129 ACPI_MADT_TYPE_LPC_PIC;
0130 struct acpi_madt_lpc_pic;
0131 enum acpi_madt_lpc_pic_version;
0132
0133 References
0134 ==========
0135
0136 Documentation of Loongson-3A5000:
0137
0138 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)
0139
0140 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)
0141
0142 Documentation of Loongson's LS7A chipset:
0143
0144 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)
0145
0146 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
0147
0148 .. Note::
0149 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
0150 in Section 7.4 of "LoongArch Reference Manual, Vol 1";
0151 - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
0152 "Loongson 3A5000 Processor Reference Manual";
0153 - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
0154 "Loongson 3A5000 Processor Reference Manual";
0155 - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
0156 "Loongson 3A5000 Processor Reference Manual";
0157 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
0158 "Loongson 7A1000 Bridge User Manual";
0159 - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
0160 "Loongson 7A1000 Bridge User Manual".
