0001 ==============================
0002 IRQ affinity on IA64 platforms
0003 ==============================
0004
0005 07.01.2002, Erich Focht <efocht@ess.nec.de>
0006
0007
0008 By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
0009 controlled. The behavior on IA64 platforms is slightly different from
0010 that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems.
0011
0012 Because of the usage of SAPIC mode and physical destination mode the
0013 IRQ target is one particular CPU and cannot be a mask of several
0014 CPUs. Only the first non-zero bit is taken into account.
0015
0016
0017 Usage examples
0018 ==============
0019
0020 The target CPU has to be specified as a hexadecimal CPU mask. The
0021 first non-zero bit is the selected CPU. This format has been kept for
0022 compatibility reasons with i386.
0023
0024 Set the delivery mode of interrupt 41 to fixed and route the
0025 interrupts to CPU #3 (logical CPU number) (2^3=0x08)::
0026
0027 echo "8" >/proc/irq/41/smp_affinity
0028
0029 Set the default route for IRQ number 41 to CPU 6 in lowest priority
0030 delivery mode (redirectable)::
0031
0032 echo "r 40" >/proc/irq/41/smp_affinity
0033
0034 The output of the command::
0035
0036 cat /proc/irq/IRQ#/smp_affinity
0037
0038 gives the target CPU mask for the specified interrupt vector. If the CPU
0039 mask is preceded by the character "r", the interrupt is redirectable
0040 (i.e. lowest priority mode routing is used), otherwise its route is
0041 fixed.
0042
0043
0044
0045 Initialization and default behavior
0046 ===================================
0047
0048 If the platform features IRQ redirection (info provided by SAL) all
0049 IO-SAPIC interrupts are initialized with CPU#0 as their default target
0050 and the routing is the so called "lowest priority mode" (actually
0051 fixed SAPIC mode with hint). The XTP chipset registers are used as hints
0052 for the IRQ routing. Currently in Linux XTP registers can have three
0053 values:
0054
0055 - minimal for an idle task,
0056 - normal if any other task runs,
0057 - maximal if the CPU is going to be switched off.
0058
0059 The IRQ is routed to the CPU with lowest XTP register value, the
0060 search begins at the default CPU. Therefore most of the interrupts
0061 will be handled by CPU #0.
0062
0063 If the platform doesn't feature interrupt redirection IOSAPIC fixed
0064 routing is used. The target CPUs are distributed in a round robin
0065 manner. IRQs will be routed only to the selected target CPUs. Check
0066 with::
0067
0068 cat /proc/interrupts
0069
0070
0071
0072 Comments
0073 ========
0074
0075 On large (multi-node) systems it is recommended to route the IRQs to
0076 the node to which the corresponding device is connected.
0077 For systems like the NEC AzusA we get IRQ node-affinity for free. This
0078 is because usually the chipsets on each node redirect the interrupts
0079 only to their own CPUs (as they cannot see the XTP registers on the
0080 other nodes).
