0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 =====================
0004 Chrome OS ACPI Device
0005 =====================
0006
0007 Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
0008 The plug and play ID of a Chrome OS ACPI device is GGL0001. GGL is a valid PNP ID of Google.
0009 PNP ID can be used with the ACPI devices according to the guidelines. The following ACPI
0010 objects are supported:
0011
0012 .. flat-table:: Supported ACPI Objects
0013 :widths: 1 2
0014 :header-rows: 1
0015
0016 * - Object
0017 - Description
0018
0019 * - CHSW
0020 - Chrome OS switch positions
0021
0022 * - HWID
0023 - Chrome OS hardware ID
0024
0025 * - FWID
0026 - Chrome OS firmware version
0027
0028 * - FRID
0029 - Chrome OS read-only firmware version
0030
0031 * - BINF
0032 - Chrome OS boot information
0033
0034 * - GPIO
0035 - Chrome OS GPIO assignments
0036
0037 * - VBNV
0038 - Chrome OS NVRAM locations
0039
0040 * - VDTA
0041 - Chrome OS verified boot data
0042
0043 * - FMAP
0044 - Chrome OS flashmap base address
0045
0046 * - MLST
0047 - Chrome OS method list
0048
0049 CHSW (Chrome OS switch positions)
0050 =================================
0051 This control method returns the switch positions for Chrome OS specific hardware switches.
0052
0053 Arguments:
0054 ----------
0055 None
0056
0057 Result code:
0058 ------------
0059 An integer containing the switch positions as bitfields:
0060
0061 .. flat-table::
0062 :widths: 1 2
0063
0064 * - 0x00000002
0065 - Recovery button was pressed when x86 firmware booted.
0066
0067 * - 0x00000004
0068 - Recovery button was pressed when EC firmware booted. (required if EC EEPROM is
0069 rewritable; otherwise optional)
0070
0071 * - 0x00000020
0072 - Developer switch was enabled when x86 firmware booted.
0073
0074 * - 0x00000200
0075 - Firmware write protection was disabled when x86 firmware booted. (required if
0076 firmware write protection is controlled through x86 BIOS; otherwise optional)
0077
0078 All other bits are reserved and should be set to 0.
0079
0080 HWID (Chrome OS hardware ID)
0081 ============================
0082 This control method returns the hardware ID for the Chromebook.
0083
0084 Arguments:
0085 ----------
0086 None
0087
0088 Result code:
0089 ------------
0090 A null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of
0091 EEPROM.
0092
0093 Note that the hardware ID can be up to 256 characters long, including the terminating null.
0094
0095 FWID (Chrome OS firmware version)
0096 =================================
0097 This control method returns the firmware version for the rewritable portion of the main
0098 processor firmware.
0099
0100 Arguments:
0101 ----------
0102 None
0103
0104 Result code:
0105 ------------
0106 A null-terminated ASCII string containing the complete firmware version for the rewritable
0107 portion of the main processor firmware.
0108
0109 FRID (Chrome OS read-only firmware version)
0110 ===========================================
0111 This control method returns the firmware version for the read-only portion of the main
0112 processor firmware.
0113
0114 Arguments:
0115 ----------
0116 None
0117
0118 Result code:
0119 ------------
0120 A null-terminated ASCII string containing the complete firmware version for the read-only
0121 (bootstrap + recovery ) portion of the main processor firmware.
0122
0123 BINF (Chrome OS boot information)
0124 =================================
0125 This control method returns information about the current boot.
0126
0127 Arguments:
0128 ----------
0129 None
0130
0131 Result code:
0132 ------------
0133
0134 .. code-block::
0135
0136 Package {
0137 Reserved1
0138 Reserved2
0139 Active EC Firmware
0140 Active Main Firmware Type
0141 Reserved5
0142 }
0143
0144 .. flat-table::
0145 :widths: 1 1 2
0146 :header-rows: 1
0147
0148 * - Field
0149 - Format
0150 - Description
0151
0152 * - Reserved1
0153 - DWORD
0154 - Set to 256 (0x100). This indicates this field is no longer used.
0155
0156 * - Reserved2
0157 - DWORD
0158 - Set to 256 (0x100). This indicates this field is no longer used.
0159
0160 * - Active EC firmware
0161 - DWORD
0162 - The EC firmware which was used during boot.
0163
0164 - 0 - Read-only (recovery) firmware
0165 - 1 - Rewritable firmware.
0166
0167 Set to 0 if EC firmware is always read-only.
0168
0169 * - Active Main Firmware Type
0170 - DWORD
0171 - The main firmware type which was used during boot.
0172
0173 - 0 - Recovery
0174 - 1 - Normal
0175 - 2 - Developer
0176 - 3 - netboot (factory installation only)
0177
0178 Other values are reserved.
0179
0180 * - Reserved5
0181 - DWORD
0182 - Set to 256 (0x100). This indicates this field is no longer used.
0183
0184 GPIO (Chrome OS GPIO assignments)
0185 =================================
0186 This control method returns information about Chrome OS specific GPIO assignments for
0187 Chrome OS hardware, so the kernel can directly control that hardware.
0188
0189 Arguments:
0190 ----------
0191 None
0192
0193 Result code:
0194 ------------
0195 .. code-block::
0196
0197 Package {
0198 Package {
0199 // First GPIO assignment
0200 Signal Type //DWORD
0201 Attributes //DWORD
0202 Controller Offset //DWORD
0203 Controller Name //ASCIIZ
0204 },
0205 ...
0206 Package {
0207 // Last GPIO assignment
0208 Signal Type //DWORD
0209 Attributes //DWORD
0210 Controller Offset //DWORD
0211 Controller Name //ASCIIZ
0212 }
0213 }
0214
0215 Where ASCIIZ means a null-terminated ASCII string.
0216
0217 .. flat-table::
0218 :widths: 1 1 2
0219 :header-rows: 1
0220
0221 * - Field
0222 - Format
0223 - Description
0224
0225 * - Signal Type
0226 - DWORD
0227 - Type of GPIO signal
0228
0229 - 0x00000001 - Recovery button
0230 - 0x00000002 - Developer mode switch
0231 - 0x00000003 - Firmware write protection switch
0232 - 0x00000100 - Debug header GPIO 0
0233 - ...
0234 - 0x000001FF - Debug header GPIO 255
0235
0236 Other values are reserved.
0237
0238 * - Attributes
0239 - DWORD
0240 - Signal attributes as bitfields:
0241
0242 - 0x00000001 - Signal is active-high (for button, a GPIO value
0243 of 1 means the button is pressed; for switches, a GPIO value
0244 of 1 means the switch is enabled). If this bit is 0, the signal
0245 is active low. Set to 0 for debug header GPIOs.
0246
0247 * - Controller Offset
0248 - DWORD
0249 - GPIO number on the specified controller.
0250
0251 * - Controller Name
0252 - ASCIIZ
0253 - Name of the controller for the GPIO.
0254 Currently supported names:
0255 "NM10" - Intel NM10 chip
0256
0257 VBNV (Chrome OS NVRAM locations)
0258 ================================
0259 This control method returns information about the NVRAM (CMOS) locations used to
0260 communicate with the BIOS.
0261
0262 Arguments:
0263 ----------
0264 None
0265
0266 Result code:
0267 ------------
0268 .. code-block::
0269
0270 Package {
0271 NV Storage Block Offset //DWORD
0272 NV Storage Block Size //DWORD
0273 }
0274
0275 .. flat-table::
0276 :widths: 1 1 2
0277 :header-rows: 1
0278
0279 * - Field
0280 - Format
0281 - Description
0282
0283 * - NV Storage Block Offset
0284 - DWORD
0285 - Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from
0286 the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of
0287 clock data).
0288
0289 * - NV Storage Block Size
0290 - DWORD
0291 - Size in bytes of the verified boot non-volatile storage block.
0292
0293 FMAP (Chrome OS flashmap address)
0294 =================================
0295 This control method returns the physical memory address of the start of the main processor
0296 firmware flashmap.
0297
0298 Arguments:
0299 ----------
0300 None
0301
0302 NoneResult code:
0303 ----------------
0304 A DWORD containing the physical memory address of the start of the main processor firmware
0305 flashmap.
0306
0307 VDTA (Chrome OS verified boot data)
0308 ===================================
0309 This control method returns the verified boot data block shared between the firmware
0310 verification step and the kernel verification step.
0311
0312 Arguments:
0313 ----------
0314 None
0315
0316 Result code:
0317 ------------
0318 A buffer containing the verified boot data block.
0319
0320 MECK (Management Engine Checksum)
0321 =================================
0322 This control method returns the SHA-1 or SHA-256 hash that is read out of the Management
0323 Engine extended registers during boot. The hash is exported via ACPI so the OS can verify that
0324 the ME firmware has not changed. If Management Engine is not present, or if the firmware was
0325 unable to read the extended registers, this buffer can be zero.
0326
0327 Arguments:
0328 ----------
0329 None
0330
0331 Result code:
0332 ------------
0333 A buffer containing the ME hash.
0334
0335 MLST (Chrome OS method list)
0336 ============================
0337 This control method returns a list of the other control methods supported by the Chrome OS
0338 hardware device.
0339
0340 Arguments:
0341 ----------
0342 None
0343
0344 Result code:
0345 ------------
0346 A package containing a list of null-terminated ASCII strings, one for each control method
0347 supported by the Chrome OS hardware device, not including the MLST method itself.
0348 For this version of the specification, the result is:
0349
0350 .. code-block::
0351
0352 Package {
0353 "CHSW",
0354 "FWID",
0355 "HWID",
0356 "FRID",
0357 "BINF",
0358 "GPIO",
0359 "VBNV",
0360 "FMAP",
0361 "VDTA",
0362 "MECK"
0363 }
