0001 .. SPDX-License-Identifier: GPL-2.0
0002
0003 ========================================
0004 GPMC (General Purpose Memory Controller)
0005 ========================================
0006
0007 GPMC is an unified memory controller dedicated to interfacing external
0008 memory devices like
0009
0010 * Asynchronous SRAM like memories and application specific integrated
0011 circuit devices.
0012 * Asynchronous, synchronous, and page mode burst NOR flash devices
0013 NAND flash
0014 * Pseudo-SRAM devices
0015
0016 GPMC is found on Texas Instruments SoC's (OMAP based)
0017 IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
0018
0019
0020 GPMC generic timing calculation:
0021 ================================
0022
0023 GPMC has certain timings that has to be programmed for proper
0024 functioning of the peripheral, while peripheral has another set of
0025 timings. To have peripheral work with gpmc, peripheral timings has to
0026 be translated to the form gpmc can understand. The way it has to be
0027 translated depends on the connected peripheral. Also there is a
0028 dependency for certain gpmc timings on gpmc clock frequency. Hence a
0029 generic timing routine was developed to achieve above requirements.
0030
0031 Generic routine provides a generic method to calculate gpmc timings
0032 from gpmc peripheral timings. struct gpmc_device_timings fields has to
0033 be updated with timings from the datasheet of the peripheral that is
0034 connected to gpmc. A few of the peripheral timings can be fed either
0035 in time or in cycles, provision to handle this scenario has been
0036 provided (refer struct gpmc_device_timings definition). It may so
0037 happen that timing as specified by peripheral datasheet is not present
0038 in timing structure, in this scenario, try to correlate peripheral
0039 timing to the one available. If that doesn't work, try to add a new
0040 field as required by peripheral, educate generic timing routine to
0041 handle it, make sure that it does not break any of the existing.
0042 Then there may be cases where peripheral datasheet doesn't mention
0043 certain fields of struct gpmc_device_timings, zero those entries.
0044
0045 Generic timing routine has been verified to work properly on
0046 multiple onenand's and tusb6010 peripherals.
0047
0048 A word of caution: generic timing routine has been developed based
0049 on understanding of gpmc timings, peripheral timings, available
0050 custom timing routines, a kind of reverse engineering without
0051 most of the datasheets & hardware (to be exact none of those supported
0052 in mainline having custom timing routine) and by simulation.
0053
0054 gpmc timing dependency on peripheral timings:
0055
0056 [<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...]
0057
0058 1. common
0059
0060 cs_on:
0061 t_ceasu
0062 adv_on:
0063 t_avdasu, t_ceavd
0064
0065 2. sync common
0066
0067 sync_clk:
0068 clk
0069 page_burst_access:
0070 t_bacc
0071 clk_activation:
0072 t_ces, t_avds
0073
0074 3. read async muxed
0075
0076 adv_rd_off:
0077 t_avdp_r
0078 oe_on:
0079 t_oeasu, t_aavdh
0080 access:
0081 t_iaa, t_oe, t_ce, t_aa
0082 rd_cycle:
0083 t_rd_cycle, t_cez_r, t_oez
0084
0085 4. read async non-muxed
0086
0087 adv_rd_off:
0088 t_avdp_r
0089 oe_on:
0090 t_oeasu
0091 access:
0092 t_iaa, t_oe, t_ce, t_aa
0093 rd_cycle:
0094 t_rd_cycle, t_cez_r, t_oez
0095
0096 5. read sync muxed
0097
0098 adv_rd_off:
0099 t_avdp_r, t_avdh
0100 oe_on:
0101 t_oeasu, t_ach, cyc_aavdh_oe
0102 access:
0103 t_iaa, cyc_iaa, cyc_oe
0104 rd_cycle:
0105 t_cez_r, t_oez, t_ce_rdyz
0106
0107 6. read sync non-muxed
0108
0109 adv_rd_off:
0110 t_avdp_r
0111 oe_on:
0112 t_oeasu
0113 access:
0114 t_iaa, cyc_iaa, cyc_oe
0115 rd_cycle:
0116 t_cez_r, t_oez, t_ce_rdyz
0117
0118 7. write async muxed
0119
0120 adv_wr_off:
0121 t_avdp_w
0122 we_on, wr_data_mux_bus:
0123 t_weasu, t_aavdh, cyc_aavhd_we
0124 we_off:
0125 t_wpl
0126 cs_wr_off:
0127 t_wph
0128 wr_cycle:
0129 t_cez_w, t_wr_cycle
0130
0131 8. write async non-muxed
0132
0133 adv_wr_off:
0134 t_avdp_w
0135 we_on, wr_data_mux_bus:
0136 t_weasu
0137 we_off:
0138 t_wpl
0139 cs_wr_off:
0140 t_wph
0141 wr_cycle:
0142 t_cez_w, t_wr_cycle
0143
0144 9. write sync muxed
0145
0146 adv_wr_off:
0147 t_avdp_w, t_avdh
0148 we_on, wr_data_mux_bus:
0149 t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we
0150 we_off:
0151 t_wpl, cyc_wpl
0152 cs_wr_off:
0153 t_wph
0154 wr_cycle:
0155 t_cez_w, t_ce_rdyz
0156
0157 10. write sync non-muxed
0158
0159 adv_wr_off:
0160 t_avdp_w
0161 we_on, wr_data_mux_bus:
0162 t_weasu, t_rdyo
0163 we_off:
0164 t_wpl, cyc_wpl
0165 cs_wr_off:
0166 t_wph
0167 wr_cycle:
0168 t_cez_w, t_ce_rdyz
0169
0170
0171 Note:
0172 Many of gpmc timings are dependent on other gpmc timings (a few
0173 gpmc timings purely dependent on other gpmc timings, a reason that
0174 some of the gpmc timings are missing above), and it will result in
0175 indirect dependency of peripheral timings to gpmc timings other than
0176 mentioned above, refer timing routine for more details. To know what
0177 these peripheral timings correspond to, please see explanations in
0178 struct gpmc_device_timings definition. And for gpmc timings refer
0179 IP details (link above).
