0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
0002 # Copyright (C) 2019--2020 Intel Corporation
0003
0004 # register rflags
0005 # - f field LSB MSB rflags
0006 # - e enum value # after a field
0007 # - e enum value [LSB MSB]
0008 # - b bool bit
0009 # - l arg name min max elsize [discontig...]
0010 #
0011 # rflags
0012 # 8, 16, 32 register bits (default is 8)
0013 # v1.1 defined in version 1.1
0014 # f formula
0015 # float_ireal iReal or IEEE 754; 32 bits
0016 # ireal unsigned iReal
0017
0018 # general status registers
0019 module_model_id 0x0000 16
0020 module_revision_number_major 0x0002 8
0021 frame_count 0x0005 8
0022 pixel_order 0x0006 8
0023 - e GRBG 0
0024 - e RGGB 1
0025 - e BGGR 2
0026 - e GBRG 3
0027 MIPI_CCS_version 0x0007 8
0028 - e v1_0 0x10
0029 - e v1_1 0x11
0030 - f major 4 7
0031 - f minor 0 3
0032 data_pedestal 0x0008 16
0033 module_manufacturer_id 0x000e 16
0034 module_revision_number_minor 0x0010 8
0035 module_date_year 0x0012 8
0036 module_date_month 0x0013 8
0037 module_date_day 0x0014 8
0038 module_date_phase 0x0015 8
0039 - f 0 2
0040 - e ts 0
0041 - e es 1
0042 - e cs 2
0043 - e mp 3
0044 sensor_model_id 0x0016 16
0045 sensor_revision_number 0x0018 8
0046 sensor_firmware_version 0x001a 8
0047 serial_number 0x001c 32
0048 sensor_manufacturer_id 0x0020 16
0049 sensor_revision_number_16 0x0022 16
0050
0051 # frame format description registers
0052 frame_format_model_type 0x0040 8
0053 - e 2-byte 1
0054 - e 4-byte 2
0055 frame_format_model_subtype 0x0041 8
0056 - f rows 0 3
0057 - f columns 4 7
0058 frame_format_descriptor(n) 0x0042 16 f
0059 - l n 0 14 2
0060 - f pixels 0 11
0061 - f pcode 12 15
0062 - e embedded 1
0063 - e dummy_pixel 2
0064 - e black_pixel 3
0065 - e dark_pixel 4
0066 - e visible_pixel 5
0067 - e manuf_specific_0 8
0068 - e manuf_specific_1 9
0069 - e manuf_specific_2 10
0070 - e manuf_specific_3 11
0071 - e manuf_specific_4 12
0072 - e manuf_specific_5 13
0073 - e manuf_specific_6 14
0074 frame_format_descriptor_4(n) 0x0060 32 f
0075 - l n 0 7 4
0076 - f pixels 0 15
0077 - f pcode 28 31
0078 - e embedded 1
0079 - e dummy_pixel 2
0080 - e black_pixel 3
0081 - e dark_pixel 4
0082 - e visible_pixel 5
0083 - e manuf_specific_0 8
0084 - e manuf_specific_1 9
0085 - e manuf_specific_2 10
0086 - e manuf_specific_3 11
0087 - e manuf_specific_4 12
0088 - e manuf_specific_5 13
0089 - e manuf_specific_6 14
0090
0091 # analog gain description registers
0092 analog_gain_capability 0x0080 16
0093 - e global 0
0094 - e alternate_global 2
0095 analog_gain_code_min 0x0084 16
0096 analog_gain_code_max 0x0086 16
0097 analog_gain_code_step 0x0088 16
0098 analog_gain_type 0x008a 16
0099 analog_gain_m0 0x008c 16
0100 analog_gain_c0 0x008e 16
0101 analog_gain_m1 0x0090 16
0102 analog_gain_c1 0x0092 16
0103 analog_linear_gain_min 0x0094 16 v1.1
0104 analog_linear_gain_max 0x0096 16 v1.1
0105 analog_linear_gain_step_size 0x0098 16 v1.1
0106 analog_exponential_gain_min 0x009a 16 v1.1
0107 analog_exponential_gain_max 0x009c 16 v1.1
0108 analog_exponential_gain_step_size 0x009e 16 v1.1
0109
0110 # data format description registers
0111 data_format_model_type 0x00c0 8
0112 - e normal 1
0113 - e extended 2
0114 data_format_model_subtype 0x00c1 8
0115 - f rows 0 3
0116 - f columns 4 7
0117 data_format_descriptor(n) 0x00c2 16 f
0118 - l n 0 15 2
0119 - f compressed 0 7
0120 - f uncompressed 8 15
0121
0122 # general set-up registers
0123 mode_select 0x0100 8
0124 - e software_standby 0
0125 - e streaming 1
0126 image_orientation 0x0101 8
0127 - b horizontal_mirror 0
0128 - b vertical_flip 1
0129 software_reset 0x0103 8
0130 - e off 0
0131 - e on 1
0132 grouped_parameter_hold 0x0104 8
0133 mask_corrupted_frames 0x0105 8
0134 - e allow 0
0135 - e mask 1
0136 fast_standby_ctrl 0x0106 8
0137 - e complete_frames 0
0138 - e frame_truncation 1
0139 CCI_address_ctrl 0x0107 8
0140 2nd_CCI_if_ctrl 0x0108 8
0141 - b enable 0
0142 - b ack 1
0143 2nd_CCI_address_ctrl 0x0109 8
0144 CSI_channel_identifier 0x0110 8
0145 CSI_signaling_mode 0x0111 8
0146 - e csi_2_dphy 2
0147 - e csi_2_cphy 3
0148 CSI_data_format 0x0112 16
0149 CSI_lane_mode 0x0114 8
0150 DPCM_Frame_DT 0x011d 8
0151 Bottom_embedded_data_DT 0x011e 8
0152 Bottom_embedded_data_VC 0x011f 8
0153
0154 gain_mode 0x0120 8
0155 - e global 0
0156 - e alternate 1
0157 ADC_bit_depth 0x0121 8
0158 emb_data_ctrl 0x0122 v1.1
0159 - b raw8_packing_for_raw16 0
0160 - b raw10_packing_for_raw20 1
0161 - b raw12_packing_for_raw24 2
0162
0163 GPIO_TRIG_mode 0x0130 8
0164 extclk_frequency_mhz 0x0136 16 ireal
0165 temp_sensor_ctrl 0x0138 8
0166 - b enable 0
0167 temp_sensor_mode 0x0139 8
0168 temp_sensor_output 0x013a 8
0169
0170 # integration time registers
0171 fine_integration_time 0x0200 16
0172 coarse_integration_time 0x0202 16
0173
0174 # analog gain registers
0175 analog_gain_code_global 0x0204 16
0176 analog_linear_gain_global 0x0206 16 v1.1
0177 analog_exponential_gain_global 0x0208 16 v1.1
0178
0179 # digital gain registers
0180 digital_gain_global 0x020e 16
0181
0182 # hdr control registers
0183 Short_analog_gain_global 0x0216 16
0184 Short_digital_gain_global 0x0218 16
0185
0186 HDR_mode 0x0220 8
0187 - b enabled 0
0188 - b separate_analog_gain 1
0189 - b upscaling 2
0190 - b reset_sync 3
0191 - b timing_mode 4
0192 - b exposure_ctrl_direct 5
0193 - b separate_digital_gain 6
0194 HDR_resolution_reduction 0x0221 8
0195 - f row 0 3
0196 - f column 4 7
0197 Exposure_ratio 0x0222 8
0198 HDR_internal_bit_depth 0x0223 8
0199 Direct_short_integration_time 0x0224 16
0200 Short_analog_linear_gain_global 0x0226 16 v1.1
0201 Short_analog_exponential_gain_global 0x0228 16 v1.1
0202
0203 # clock set-up registers
0204 vt_pix_clk_div 0x0300 16
0205 vt_sys_clk_div 0x0302 16
0206 pre_pll_clk_div 0x0304 16
0207 #vt_pre_pll_clk_div 0x0304 16
0208 pll_multiplier 0x0306 16
0209 #vt_pll_multiplier 0x0306 16
0210 op_pix_clk_div 0x0308 16
0211 op_sys_clk_div 0x030a 16
0212 op_pre_pll_clk_div 0x030c 16
0213 op_pll_multiplier 0x030e 16
0214 pll_mode 0x0310 8
0215 - f 0 0
0216 - e single 0
0217 - e dual 1
0218 op_pix_clk_div_rev 0x0312 16 v1.1
0219 op_sys_clk_div_rev 0x0314 16 v1.1
0220
0221 # frame timing registers
0222 frame_length_lines 0x0340 16
0223 line_length_pck 0x0342 16
0224
0225 # image size registers
0226 x_addr_start 0x0344 16
0227 y_addr_start 0x0346 16
0228 x_addr_end 0x0348 16
0229 y_addr_end 0x034a 16
0230 x_output_size 0x034c 16
0231 y_output_size 0x034e 16
0232
0233 # timing mode registers
0234 Frame_length_ctrl 0x0350 8
0235 - b automatic 0
0236 Timing_mode_ctrl 0x0352 8
0237 - b manual_readout 0
0238 - b delayed_exposure 1
0239 Start_readout_rs 0x0353 8
0240 - b manual_readout_start 0
0241 Frame_margin 0x0354 16
0242
0243 # sub-sampling registers
0244 x_even_inc 0x0380 16
0245 x_odd_inc 0x0382 16
0246 y_even_inc 0x0384 16
0247 y_odd_inc 0x0386 16
0248
0249 # monochrome readout registers
0250 monochrome_en 0x0390 v1.1
0251 - e enabled 0
0252
0253 # image scaling registers
0254 Scaling_mode 0x0400 16
0255 - e no_scaling 0
0256 - e horizontal 1
0257 scale_m 0x0404 16
0258 scale_n 0x0406 16
0259 digital_crop_x_offset 0x0408 16
0260 digital_crop_y_offset 0x040a 16
0261 digital_crop_image_width 0x040c 16
0262 digital_crop_image_height 0x040e 16
0263
0264 # image compression registers
0265 compression_mode 0x0500 16
0266 - e none 0
0267 - e dpcm_pcm_simple 1
0268
0269 # test pattern registers
0270 test_pattern_mode 0x0600 16
0271 - e none 0
0272 - e solid_color 1
0273 - e color_bars 2
0274 - e fade_to_grey 3
0275 - e pn9 4
0276 - e color_tile 5
0277 test_data_red 0x0602 16
0278 test_data_greenR 0x0604 16
0279 test_data_blue 0x0606 16
0280 test_data_greenB 0x0608 16
0281 value_step_size_smooth 0x060a 8
0282 value_step_size_quantised 0x060b 8
0283
0284 # phy configuration registers
0285 tclk_post 0x0800 8
0286 ths_prepare 0x0801 8
0287 ths_zero_min 0x0802 8
0288 ths_trail 0x0803 8
0289 tclk_trail_min 0x0804 8
0290 tclk_prepare 0x0805 8
0291 tclk_zero 0x0806 8
0292 tlpx 0x0807 8
0293 phy_ctrl 0x0808 8
0294 - e auto 0
0295 - e UI 1
0296 - e manual 2
0297 tclk_post_ex 0x080a 16
0298 ths_prepare_ex 0x080c 16
0299 ths_zero_min_ex 0x080e 16
0300 ths_trail_ex 0x0810 16
0301 tclk_trail_min_ex 0x0812 16
0302 tclk_prepare_ex 0x0814 16
0303 tclk_zero_ex 0x0816 16
0304 tlpx_ex 0x0818 16
0305
0306 # link rate register
0307 requested_link_rate 0x0820 32 u16.16
0308
0309 # equalization control registers
0310 DPHY_equalization_mode 0x0824 8 v1.1
0311 - b eq2 0
0312 PHY_equalization_ctrl 0x0825 8 v1.1
0313 - b enable 0
0314
0315 # d-phy preamble control registers
0316 DPHY_preamble_ctrl 0x0826 8 v1.1
0317 - b enable 0
0318 DPHY_preamble_length 0x0826 8 v1.1
0319
0320 # d-phy spread spectrum control registers
0321 PHY_SSC_ctrl 0x0828 8 v1.1
0322 - b enable 0
0323
0324 # manual lp control register
0325 manual_LP_ctrl 0x0829 8 v1.1
0326 - b enable 0
0327
0328 # additional phy configuration registers
0329 twakeup 0x082a v1.1
0330 tinit 0x082b v1.1
0331 ths_exit 0x082c v1.1
0332 ths_exit_ex 0x082e 16 v1.1
0333
0334 # phy calibration configuration registers
0335 PHY_periodic_calibration_ctrl 0x0830 8
0336 - b frame_blanking 0
0337 PHY_periodic_calibration_interval 0x0831 8
0338 PHY_init_calibration_ctrl 0x0832 8
0339 - b stream_start 0
0340 DPHY_calibration_mode 0x0833 8 v1.1
0341 - b also_alternate 0
0342 CPHY_calibration_mode 0x0834 8 v1.1
0343 - e format_1 0
0344 - e format_2 1
0345 - e format_3 2
0346 t3_calpreamble_length 0x0835 8 v1.1
0347 t3_calpreamble_length_per 0x0836 8 v1.1
0348 t3_calaltseq_length 0x0837 8 v1.1
0349 t3_calaltseq_length_per 0x0838 8 v1.1
0350 FM2_init_seed 0x083a 16 v1.1
0351 t3_caludefseq_length 0x083c 16 v1.1
0352 t3_caludefseq_length_per 0x083e 16 v1.1
0353
0354 # c-phy manual control registers
0355 TGR_Preamble_Length 0x0841 8
0356 - b preamable_prog_seq 7
0357 - f begin_preamble_length 0 5
0358 TGR_Post_Length 0x0842 8
0359 - f post_length 0 4
0360 TGR_Preamble_Prog_Sequence(n2) 0x0843
0361 - l n2 0 6 1
0362 - f symbol_n_1 3 5
0363 - f symbol_n 0 2
0364 t3_prepare 0x084e 16
0365 t3_lpx 0x0850 16
0366
0367 # alps control register
0368 ALPS_ctrl 0x085a 8
0369 - b lvlp_dphy 0
0370 - b lvlp_cphy 1
0371 - b alp_cphy 2
0372
0373 # lrte control registers
0374 TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16
0375 TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16
0376 TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16
0377 TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16
0378 TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
0379 TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
0380
0381 # scrambling control registers
0382 Scrambling_ctrl 0x0870
0383 - b enabled 0
0384 - f 2 3
0385 - e 1_seed_cphy 0
0386 - e 4_seed_cphy 3
0387 lane_seed_value(seed, lane) 0x0872 16
0388 - l seed 0 3 0x10
0389 - l lane 0 7 0x2
0390
0391 # usl control registers
0392 TX_USL_REV_ENTRY 0x08c0 16 v1.1
0393 TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
0394 TX_USL_REV_LP_Counter 0x08c4 16 v1.1
0395 TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
0396 TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
0397 TX_USL_FWD_ENTRY 0x08ca 16 v1.1
0398 TX_USL_GPIO 0x08cc 16 v1.1
0399 TX_USL_Operation 0x08ce 16 v1.1
0400 - b reset 0
0401 TX_USL_ALP_ctrl 0x08d0 16 v1.1
0402 - b clock_pause 0
0403 TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
0404 TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
0405 USL_Clock_Mode_d_ctrl 0x08d2 v1.1
0406 - b cont_clock_standby 0
0407 - b cont_clock_vblank 1
0408 - b cont_clock_hblank 2
0409
0410 # binning configuration registers
0411 binning_mode 0x0900 8
0412 binning_type 0x0901 8
0413 binning_weighting 0x0902 8
0414
0415 # data transfer interface registers
0416 data_transfer_if_1_ctrl 0x0a00 8
0417 - b enable 0
0418 - b write 1
0419 - b clear_error 2
0420 data_transfer_if_1_status 0x0a01 8
0421 - b read_if_ready 0
0422 - b write_if_ready 1
0423 - b data_corrupted 2
0424 - b improper_if_usage 3
0425 data_transfer_if_1_page_select 0x0a02 8
0426 data_transfer_if_1_data(p) 0x0a04 8 f
0427 - l p 0 63 1
0428
0429 # image processing and sensor correction configuration registers
0430 shading_correction_en 0x0b00 8
0431 - b enable 0
0432 luminance_correction_level 0x0b01 8
0433 green_imbalance_filter_en 0x0b02 8
0434 - b enable 0
0435 mapped_defect_correct_en 0x0b05 8
0436 - b enable 0
0437 single_defect_correct_en 0x0b06 8
0438 - b enable 0
0439 dynamic_couplet_correct_en 0x0b08 8
0440 - b enable 0
0441 combined_defect_correct_en 0x0b0a 8
0442 - b enable 0
0443 module_specific_correction_en 0x0b0c 8
0444 - b enable 0
0445 dynamic_triplet_defect_correct_en 0x0b13 8
0446 - b enable 0
0447 NF_ctrl 0x0b15 8
0448 - b luma 0
0449 - b chroma 1
0450 - b combined 2
0451
0452 # optical black pixel readout registers
0453 OB_readout_control 0x0b30 8
0454 - b enable 0
0455 - b interleaving 1
0456 OB_virtual_channel 0x0b31 8
0457 OB_DT 0x0b32 8
0458 OB_data_format 0x0b33 8
0459
0460 # color temperature feedback registers
0461 color_temperature 0x0b8c 16
0462 absolute_gain_greenr 0x0b8e 16
0463 absolute_gain_red 0x0b90 16
0464 absolute_gain_blue 0x0b92 16
0465 absolute_gain_greenb 0x0b94 16
0466
0467 # cfa conversion registers
0468 CFA_conversion_ctrl 0x0ba0 v1.1
0469 - b bayer_conversion_enable 0
0470
0471 # flash strobe and sa strobe control registers
0472 flash_strobe_adjustment 0x0c12 8
0473 flash_strobe_start_point 0x0c14 16
0474 tflash_strobe_delay_rs_ctrl 0x0c16 16
0475 tflash_strobe_width_high_rs_ctrl 0x0c18 16
0476 flash_mode_rs 0x0c1a 8
0477 - b continuous 0
0478 - b truncate 1
0479 - b async 3
0480 flash_trigger_rs 0x0c1b 8
0481 flash_status 0x0c1c 8
0482 - b retimed 0
0483 sa_strobe_mode 0x0c1d 8
0484 - b continuous 0
0485 - b truncate 1
0486 - b async 3
0487 - b adjust_edge 4
0488 sa_strobe_start_point 0x0c1e 16
0489 tsa_strobe_delay_ctrl 0x0c20 16
0490 tsa_strobe_width_ctrl 0x0c22 16
0491 sa_strobe_trigger 0x0c24 8
0492 sa_strobe_status 0x0c25 8
0493 - b retimed 0
0494 tSA_strobe_re_delay_ctrl 0x0c30 16
0495 tSA_strobe_fe_delay_ctrl 0x0c32 16
0496
0497 # pdaf control registers
0498 PDAF_ctrl 0x0d00 16
0499 - b enable 0
0500 - b processed 1
0501 - b interleaved 2
0502 - b visible_pdaf_correction 3
0503 PDAF_VC 0x0d02 8
0504 PDAF_DT 0x0d03 8
0505 pd_x_addr_start 0x0d04 16
0506 pd_y_addr_start 0x0d06 16
0507 pd_x_addr_end 0x0d08 16
0508 pd_y_addr_end 0x0d0a 16
0509
0510 # bracketing interface configuration registers
0511 bracketing_LUT_ctrl 0x0e00 8
0512 bracketing_LUT_mode 0x0e01 8
0513 - b continue_streaming 0
0514 - b loop_mode 1
0515 bracketing_LUT_entry_ctrl 0x0e02 8
0516 bracketing_LUT_frame(n) 0x0e10 v1.1 f
0517 - l n 0 0xef 1
0518
0519 # integration time and gain parameter limit registers
0520 integration_time_capability 0x1000 16
0521 - b fine 0
0522 coarse_integration_time_min 0x1004 16
0523 coarse_integration_time_max_margin 0x1006 16
0524 fine_integration_time_min 0x1008 16
0525 fine_integration_time_max_margin 0x100a 16
0526
0527 # digital gain parameter limit registers
0528 digital_gain_capability 0x1081
0529 - e none 0
0530 - e global 2
0531 digital_gain_min 0x1084 16
0532 digital_gain_max 0x1086 16
0533 digital_gain_step_size 0x1088 16
0534
0535 # data pedestal capability registers
0536 Pedestal_capability 0x10e0 8 v1.1
0537
0538 # adc capability registers
0539 ADC_capability 0x10f0 8
0540 - b bit_depth_ctrl 0
0541 ADC_bit_depth_capability 0x10f4 32 v1.1
0542
0543 # video timing parameter limit registers
0544 min_ext_clk_freq_mhz 0x1100 32 float_ireal
0545 max_ext_clk_freq_mhz 0x1104 32 float_ireal
0546 min_pre_pll_clk_div 0x1108 16
0547 # min_vt_pre_pll_clk_div 0x1108 16
0548 max_pre_pll_clk_div 0x110a 16
0549 # max_vt_pre_pll_clk_div 0x110a 16
0550 min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
0551 # min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
0552 max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
0553 # max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
0554 min_pll_multiplier 0x1114 16
0555 # min_vt_pll_multiplier 0x1114 16
0556 max_pll_multiplier 0x1116 16
0557 # max_vt_pll_multiplier 0x1116 16
0558 min_pll_op_clk_freq_mhz 0x1118 32 float_ireal
0559 max_pll_op_clk_freq_mhz 0x111c 32 float_ireal
0560
0561 # video timing set-up capability registers
0562 min_vt_sys_clk_div 0x1120 16
0563 max_vt_sys_clk_div 0x1122 16
0564 min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal
0565 max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal
0566 min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal
0567 max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal
0568 min_vt_pix_clk_div 0x1134 16
0569 max_vt_pix_clk_div 0x1136 16
0570 clock_calculation 0x1138
0571 - b lane_speed 0
0572 - b link_decoupled 1
0573 - b dual_pll_op_sys_ddr 2
0574 - b dual_pll_op_pix_ddr 3
0575 num_of_vt_lanes 0x1139
0576 num_of_op_lanes 0x113a
0577 op_bits_per_lane 0x113b 8 v1.1
0578
0579 # frame timing parameter limits
0580 min_frame_length_lines 0x1140 16
0581 max_frame_length_lines 0x1142 16
0582 min_line_length_pck 0x1144 16
0583 max_line_length_pck 0x1146 16
0584 min_line_blanking_pck 0x1148 16
0585 min_frame_blanking_lines 0x114a 16
0586 min_line_length_pck_step_size 0x114c
0587 timing_mode_capability 0x114d
0588 - b auto_frame_length 0
0589 - b rolling_shutter_manual_readout 2
0590 - b delayed_exposure_start 3
0591 - b manual_exposure_embedded_data 4
0592 frame_margin_max_value 0x114e 16
0593 frame_margin_min_value 0x1150
0594 gain_delay_type 0x1151
0595 - e fixed 0
0596 - e variable 1
0597
0598 # output clock set-up capability registers
0599 min_op_sys_clk_div 0x1160 16
0600 max_op_sys_clk_div 0x1162 16
0601 min_op_sys_clk_freq_mhz 0x1164 32 float_ireal
0602 max_op_sys_clk_freq_mhz 0x1168 32 float_ireal
0603 min_op_pix_clk_div 0x116c 16
0604 max_op_pix_clk_div 0x116e 16
0605 min_op_pix_clk_freq_mhz 0x1170 32 float_ireal
0606 max_op_pix_clk_freq_mhz 0x1174 32 float_ireal
0607
0608 # image size parameter limit registers
0609 x_addr_min 0x1180 16
0610 y_addr_min 0x1182 16
0611 x_addr_max 0x1184 16
0612 y_addr_max 0x1186 16
0613 min_x_output_size 0x1188 16
0614 min_y_output_size 0x118a 16
0615 max_x_output_size 0x118c 16
0616 max_y_output_size 0x118e 16
0617
0618 x_addr_start_div_constant 0x1190 v1.1
0619 y_addr_start_div_constant 0x1191 v1.1
0620 x_addr_end_div_constant 0x1192 v1.1
0621 y_addr_end_div_constant 0x1193 v1.1
0622 x_size_div 0x1194 v1.1
0623 y_size_div 0x1195 v1.1
0624 x_output_div 0x1196 v1.1
0625 y_output_div 0x1197 v1.1
0626 non_flexible_resolution_support 0x1198 v1.1
0627 - b new_pix_addr 0
0628 - b new_output_res 1
0629 - b output_crop_no_pad 2
0630 - b output_size_lane_dep 3
0631
0632 min_op_pre_pll_clk_div 0x11a0 16
0633 max_op_pre_pll_clk_div 0x11a2 16
0634 min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal
0635 max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal
0636 min_op_pll_multiplier 0x11ac 16
0637 max_op_pll_multiplier 0x11ae 16
0638 min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal
0639 max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal
0640 clock_tree_pll_capability 0x11b8 8
0641 - b dual_pll 0
0642 - b single_pll 1
0643 - b ext_divider 2
0644 - b flexible_op_pix_clk_div 3
0645 clock_capa_type_capability 0x11b9 v1.1
0646 - b ireal 0
0647
0648 # sub-sampling parameters limit registers
0649 min_even_inc 0x11c0 16
0650 min_odd_inc 0x11c2 16
0651 max_even_inc 0x11c4 16
0652 max_odd_inc 0x11c6 16
0653 aux_subsamp_capability 0x11c8 v1.1
0654 - b factor_power_of_2 1
0655 aux_subsamp_mono_capability 0x11c9 v1.1
0656 - b factor_power_of_2 1
0657 monochrome_capability 0x11ca v1.1
0658 - e inc_odd 0
0659 - e inc_even 1
0660 pixel_readout_capability 0x11cb v1.1
0661 - e bayer 0
0662 - e monochrome 1
0663 - e bayer_and_mono 2
0664 min_even_inc_mono 0x11cc 16 v1.1
0665 max_even_inc_mono 0x11ce 16 v1.1
0666 min_odd_inc_mono 0x11d0 16 v1.1
0667 max_odd_inc_mono 0x11d2 16 v1.1
0668 min_even_inc_bc2 0x11d4 16 v1.1
0669 max_even_inc_bc2 0x11d6 16 v1.1
0670 min_odd_inc_bc2 0x11d8 16 v1.1
0671 max_odd_inc_bc2 0x11da 16 v1.1
0672 min_even_inc_mono_bc2 0x11dc 16 v1.1
0673 max_even_inc_mono_bc2 0x11de 16 v1.1
0674 min_odd_inc_mono_bc2 0x11f0 16 v1.1
0675 max_odd_inc_mono_bc2 0x11f2 16 v1.1
0676
0677 # image scaling limit parameters
0678 scaling_capability 0x1200 16
0679 - e none 0
0680 - e horizontal 1
0681 - e reserved 2
0682 scaler_m_min 0x1204 16
0683 scaler_m_max 0x1206 16
0684 scaler_n_min 0x1208 16
0685 scaler_n_max 0x120a 16
0686 digital_crop_capability 0x120e
0687 - e none 0
0688 - e input_crop 1
0689
0690 # hdr limit registers
0691 hdr_capability_1 0x1210
0692 - b 2x2_binning 0
0693 - b combined_analog_gain 1
0694 - b separate_analog_gain 2
0695 - b upscaling 3
0696 - b reset_sync 4
0697 - b direct_short_exp_timing 5
0698 - b direct_short_exp_synthesis 6
0699 min_hdr_bit_depth 0x1211
0700 hdr_resolution_sub_types 0x1212
0701 hdr_resolution_sub_type(n) 0x1213
0702 - l n 0 1 1
0703 - f row 0 3
0704 - f column 4 7
0705 hdr_capability_2 0x121b
0706 - b combined_digital_gain 0
0707 - b separate_digital_gain 1
0708 - b timing_mode 3
0709 - b synthesis_mode 4
0710 max_hdr_bit_depth 0x121c
0711
0712 # usl capability register
0713 usl_support_capability 0x1230 v1.1
0714 - b clock_tree 0
0715 - b rev_clock_tree 1
0716 - b rev_clock_calc 2
0717 usl_clock_mode_d_capability 0x1231 v1.1
0718 - b cont_clock_standby 0
0719 - b cont_clock_vblank 1
0720 - b cont_clock_hblank 2
0721 - b noncont_clock_standby 3
0722 - b noncont_clock_vblank 4
0723 - b noncont_clock_hblank 5
0724 min_op_sys_clk_div_rev 0x1234 v1.1
0725 max_op_sys_clk_div_rev 0x1236 v1.1
0726 min_op_pix_clk_div_rev 0x1238 v1.1
0727 max_op_pix_clk_div_rev 0x123a v1.1
0728 min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
0729 max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
0730 min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
0731 max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
0732 max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
0733 max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
0734
0735 # image compression capability registers
0736 compression_capability 0x1300
0737 - b dpcm_pcm_simple 0
0738
0739 # test mode capability registers
0740 test_mode_capability 0x1310 16
0741 - b solid_color 0
0742 - b color_bars 1
0743 - b fade_to_grey 2
0744 - b pn9 3
0745 - b color_tile 5
0746 pn9_data_format1 0x1312
0747 pn9_data_format2 0x1313
0748 pn9_data_format3 0x1314
0749 pn9_data_format4 0x1315
0750 pn9_misc_capability 0x1316
0751 - f num_pixels 0 2
0752 - b compression 3
0753 test_pattern_capability 0x1317 v1.1
0754 - b no_repeat 1
0755 pattern_size_div_m1 0x1318 v1.1
0756
0757 # fifo capability registers
0758 fifo_support_capability 0x1502
0759 - e none 0
0760 - e derating 1
0761 - e derating_overrating 2
0762
0763 # csi-2 capability registers
0764 phy_ctrl_capability 0x1600
0765 - b auto_phy_ctl 0
0766 - b ui_phy_ctl 1
0767 - b dphy_time_ui_reg_1_ctl 2
0768 - b dphy_time_ui_reg_2_ctl 3
0769 - b dphy_time_ctl 4
0770 - b dphy_ext_time_ui_reg_1_ctl 5
0771 - b dphy_ext_time_ui_reg_2_ctl 6
0772 - b dphy_ext_time_ctl 7
0773 csi_dphy_lane_mode_capability 0x1601
0774 - b 1_lane 0
0775 - b 2_lane 1
0776 - b 3_lane 2
0777 - b 4_lane 3
0778 - b 5_lane 4
0779 - b 6_lane 5
0780 - b 7_lane 6
0781 - b 8_lane 7
0782 csi_signaling_mode_capability 0x1602
0783 - b csi_dphy 2
0784 - b csi_cphy 3
0785 fast_standby_capability 0x1603
0786 - e no_frame_truncation 0
0787 - e frame_truncation 1
0788 csi_address_control_capability 0x1604
0789 - b cci_addr_change 0
0790 - b 2nd_cci_addr 1
0791 - b sw_changeable_2nd_cci_addr 2
0792 data_type_capability 0x1605
0793 - b dpcm_programmable 0
0794 - b bottom_embedded_dt_programmable 1
0795 - b bottom_embedded_vc_programmable 2
0796 - b ext_vc_range 3
0797 csi_cphy_lane_mode_capability 0x1606
0798 - b 1_lane 0
0799 - b 2_lane 1
0800 - b 3_lane 2
0801 - b 4_lane 3
0802 - b 5_lane 4
0803 - b 6_lane 5
0804 - b 7_lane 6
0805 - b 8_lane 7
0806 emb_data_capability 0x1607 v1.1
0807 - b two_bytes_per_raw16 0
0808 - b two_bytes_per_raw20 1
0809 - b two_bytes_per_raw24 2
0810 - b no_one_byte_per_raw16 3
0811 - b no_one_byte_per_raw20 4
0812 - b no_one_byte_per_raw24 5
0813 max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal
0814 - l n 0 7 4 4,0x32
0815 temp_sensor_capability 0x1618
0816 - b supported 0
0817 - b CCS_format 1
0818 - b reset_0x80 2
0819 max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal
0820 - l n 0 7 4 4,0x30
0821 dphy_equalization_capability 0x162b
0822 - b equalization_ctrl 0
0823 - b eq1 1
0824 - b eq2 2
0825 cphy_equalization_capability 0x162c
0826 - b equalization_ctrl 0
0827 dphy_preamble_capability 0x162d
0828 - b preamble_seq_ctrl 0
0829 dphy_ssc_capability 0x162e
0830 - b supported 0
0831 cphy_calibration_capability 0x162f
0832 - b manual 0
0833 - b manual_streaming 1
0834 - b format_1_ctrl 2
0835 - b format_2_ctrl 3
0836 - b format_3_ctrl 4
0837 dphy_calibration_capability 0x1630
0838 - b manual 0
0839 - b manual_streaming 1
0840 - b alternate_seq 2
0841 phy_ctrl_capability_2 0x1631
0842 - b tgr_length 0
0843 - b tgr_preamble_prog_seq 1
0844 - b extra_cphy_manual_timing 2
0845 - b clock_based_manual_cdphy 3
0846 - b clock_based_manual_dphy 4
0847 - b clock_based_manual_cphy 5
0848 - b manual_lp_dphy 6
0849 - b manual_lp_cphy 7
0850 lrte_cphy_capability 0x1632
0851 - b pdq_short 0
0852 - b spacer_short 1
0853 - b pdq_long 2
0854 - b spacer_long 3
0855 - b spacer_no_pdq 4
0856 lrte_dphy_capability 0x1633
0857 - b pdq_short_opt1 0
0858 - b spacer_short_opt1 1
0859 - b pdq_long_opt1 2
0860 - b spacer_long_opt1 3
0861 - b spacer_short_opt2 4
0862 - b spacer_long_opt2 5
0863 - b spacer_no_pdq_opt1 6
0864 - b spacer_variable_opt2 7
0865 alps_capability_dphy 0x1634
0866 - e lvlp_not_supported 0 0x3
0867 - e lvlp_supported 1 0x3
0868 - e controllable_lvlp 2 0x3
0869 alps_capability_cphy 0x1635
0870 - e lvlp_not_supported 0 0x3
0871 - e lvlp_supported 1 0x3
0872 - e controllable_lvlp 2 0x3
0873 - e alp_not_supported 0xc 0xc
0874 - e alp_supported 0xd 0xc
0875 - e controllable_alp 0xe 0xc
0876 scrambling_capability 0x1636
0877 - b scrambling_supported 0
0878 - f max_seeds_per_lane_c 1 2
0879 - e 1 0
0880 - e 4 3
0881 - f num_seed_regs 3 5
0882 - e 0 0
0883 - e 1 1
0884 - e 4 4
0885 - b num_seed_per_lane 6
0886 dphy_manual_constant 0x1637
0887 cphy_manual_constant 0x1638
0888 CSI2_interface_capability_misc 0x1639 v1.1
0889 - b eotp_short_pkt_opt2 0
0890 PHY_ctrl_capability_3 0x165c v1.1
0891 - b dphy_timing_not_multiple 0
0892 - b dphy_min_timing_value_1 1
0893 - b twakeup_supported 2
0894 - b tinit_supported 3
0895 - b ths_exit_supported 4
0896 - b cphy_timing_not_multiple 5
0897 - b cphy_min_timing_value_1 6
0898 dphy_sf 0x165d v1.1
0899 cphy_sf 0x165e v1.1
0900 - f twakeup 0 3
0901 - f tinit 4 7
0902 dphy_limits_1 0x165f v1.1
0903 - f ths_prepare 0 3
0904 - f ths_zero 4 7
0905 dphy_limits_2 0x1660 v1.1
0906 - f ths_trail 0 3
0907 - f tclk_trail_min 4 7
0908 dphy_limits_3 0x1661 v1.1
0909 - f tclk_prepare 0 3
0910 - f tclk_zero 4 7
0911 dphy_limits_4 0x1662 v1.1
0912 - f tclk_post 0 3
0913 - f tlpx 4 7
0914 dphy_limits_5 0x1663 v1.1
0915 - f ths_exit 0 3
0916 - f twakeup 4 7
0917 dphy_limits_6 0x1664 v1.1
0918 - f tinit 0 3
0919 cphy_limits_1 0x1665 v1.1
0920 - f t3_prepare_max 0 3
0921 - f t3_lpx_max 4 7
0922 cphy_limits_2 0x1666 v1.1
0923 - f ths_exit_max 0 3
0924 - f twakeup_max 4 7
0925 cphy_limits_3 0x1667 v1.1
0926 - f tinit_max 0 3
0927
0928 # binning capability registers
0929 min_frame_length_lines_bin 0x1700 16
0930 max_frame_length_lines_bin 0x1702 16
0931 min_line_length_pck_bin 0x1704 16
0932 max_line_length_pck_bin 0x1706 16
0933 min_line_blanking_pck_bin 0x1708 16
0934 fine_integration_time_min_bin 0x170a 16
0935 fine_integration_time_max_margin_bin 0x170c 16
0936 binning_capability 0x1710
0937 - e unsupported 0
0938 - e binning_then_subsampling 1
0939 - e subsampling_then_binning 2
0940 binning_weighting_capability 0x1711
0941 - b averaged 0
0942 - b summed 1
0943 - b bayer_corrected 2
0944 - b module_specific_weight 3
0945 binning_sub_types 0x1712
0946 binning_sub_type(n) 0x1713
0947 - l n 0 63 1
0948 - f row 0 3
0949 - f column 4 7
0950 binning_weighting_mono_capability 0x1771 v1.1
0951 - b averaged 0
0952 - b summed 1
0953 - b bayer_corrected 2
0954 - b module_specific_weight 3
0955 binning_sub_types_mono 0x1772 v1.1
0956 binning_sub_type_mono(n) 0x1773 v1.1 f
0957 - l n 0 63 1
0958
0959 # data transfer interface capability registers
0960 data_transfer_if_capability 0x1800
0961 - b supported 0
0962 - b polling 2
0963
0964 # sensor correction capability registers
0965 shading_correction_capability 0x1900
0966 - b color_shading 0
0967 - b luminance_correction 1
0968 green_imbalance_capability 0x1901
0969 - b supported 0
0970 module_specific_correction_capability 0x1903
0971 defect_correction_capability 0x1904 16
0972 - b mapped_defect 0
0973 - b dynamic_couplet 2
0974 - b dynamic_single 5
0975 - b combined_dynamic 8
0976 defect_correction_capability_2 0x1906 16
0977 - b dynamic_triplet 3
0978 nf_capability 0x1908
0979 - b luma 0
0980 - b chroma 1
0981 - b combined 2
0982
0983 # optical black readout capability registers
0984 ob_readout_capability 0x1980
0985 - b controllable_readout 0
0986 - b visible_pixel_readout 1
0987 - b different_vc_readout 2
0988 - b different_dt_readout 3
0989 - b prog_data_format 4
0990
0991 # color feedback capability registers
0992 color_feedback_capability 0x1987
0993 - b kelvin 0
0994 - b awb_gain 1
0995
0996 # cfa pattern capability registers
0997 CFA_pattern_capability 0x1990 v1.1
0998 - e bayer 0
0999 - e monochrome 1
1000 - e 4x4_quad_bayer 2
1001 - e vendor_specific 3
1002 CFA_pattern_conversion_capability 0x1991 v1.1
1003 - b bayer 0
1004
1005 # timer capability registers
1006 flash_mode_capability 0x1a02
1007 - b single_strobe 0
1008 sa_strobe_mode_capability 0x1a03
1009 - b fixed_width 0
1010 - b edge_ctrl 1
1011
1012 # soft reset capability registers
1013 reset_max_delay 0x1a10 v1.1
1014 reset_min_time 0x1a11 v1.1
1015
1016 # pdaf capability registers
1017 pdaf_capability_1 0x1b80
1018 - b supported 0
1019 - b processed_bottom_embedded 1
1020 - b processed_interleaved 2
1021 - b raw_bottom_embedded 3
1022 - b raw_interleaved 4
1023 - b visible_pdaf_correction 5
1024 - b vc_interleaving 6
1025 - b dt_interleaving 7
1026 pdaf_capability_2 0x1b81
1027 - b ROI 0
1028 - b after_digital_crop 1
1029 - b ctrl_retimed 2
1030
1031 # bracketing interface capability registers
1032 bracketing_lut_capability_1 0x1c00
1033 - b coarse_integration 0
1034 - b global_analog_gain 1
1035 - b flash 4
1036 - b global_digital_gain 5
1037 - b alternate_global_analog_gain 6
1038 bracketing_lut_capability_2 0x1c01
1039 - b single_bracketing_mode 0
1040 - b looped_bracketing_mode 1
1041 bracketing_lut_size 0x1c02
