Back to home page

OSCL-LXR

 
 

    


0001 FPGA Manager
0002 ============
0003 
0004 Overview
0005 --------
0006 
0007 The FPGA manager core exports a set of functions for programming an FPGA with
0008 an image.  The API is manufacturer agnostic.  All manufacturer specifics are
0009 hidden away in a low level driver which registers a set of ops with the core.
0010 The FPGA image data itself is very manufacturer specific, but for our purposes
0011 it's just binary data.  The FPGA manager core won't parse it.
0012 
0013 The FPGA image to be programmed can be in a scatter gather list, a single
0014 contiguous buffer, or a firmware file.  Because allocating contiguous kernel
0015 memory for the buffer should be avoided, users are encouraged to use a scatter
0016 gather list instead if possible.
0017 
0018 The particulars for programming the image are presented in a structure (struct
0019 fpga_image_info).  This struct contains parameters such as pointers to the
0020 FPGA image as well as image-specific particulars such as whether the image was
0021 built for full or partial reconfiguration.
0022 
0023 How to support a new FPGA device
0024 --------------------------------
0025 
0026 To add another FPGA manager, write a driver that implements a set of ops.  The
0027 probe function calls fpga_mgr_register() or fpga_mgr_register_full(), such as::
0028 
0029         static const struct fpga_manager_ops socfpga_fpga_ops = {
0030                 .write_init = socfpga_fpga_ops_configure_init,
0031                 .write = socfpga_fpga_ops_configure_write,
0032                 .write_complete = socfpga_fpga_ops_configure_complete,
0033                 .state = socfpga_fpga_ops_state,
0034         };
0035 
0036         static int socfpga_fpga_probe(struct platform_device *pdev)
0037         {
0038                 struct device *dev = &pdev->dev;
0039                 struct socfpga_fpga_priv *priv;
0040                 struct fpga_manager *mgr;
0041                 int ret;
0042 
0043                 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0044                 if (!priv)
0045                         return -ENOMEM;
0046 
0047                 /*
0048                  * do ioremaps, get interrupts, etc. and save
0049                  * them in priv
0050                  */
0051 
0052                 mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
0053                                         &socfpga_fpga_ops, priv);
0054                 if (IS_ERR(mgr))
0055                         return PTR_ERR(mgr);
0056 
0057                 platform_set_drvdata(pdev, mgr);
0058 
0059                 return 0;
0060         }
0061 
0062         static int socfpga_fpga_remove(struct platform_device *pdev)
0063         {
0064                 struct fpga_manager *mgr = platform_get_drvdata(pdev);
0065 
0066                 fpga_mgr_unregister(mgr);
0067 
0068                 return 0;
0069         }
0070 
0071 Alternatively, the probe function could call one of the resource managed
0072 register functions, devm_fpga_mgr_register() or devm_fpga_mgr_register_full().
0073 When these functions are used, the parameter syntax is the same, but the call
0074 to fpga_mgr_unregister() should be removed. In the above example, the
0075 socfpga_fpga_remove() function would not be required.
0076 
0077 The ops will implement whatever device specific register writes are needed to
0078 do the programming sequence for this particular FPGA.  These ops return 0 for
0079 success or negative error codes otherwise.
0080 
0081 The programming sequence is::
0082  1. .parse_header (optional, may be called once or multiple times)
0083  2. .write_init
0084  3. .write or .write_sg (may be called once or multiple times)
0085  4. .write_complete
0086 
0087 The .parse_header function will set header_size and data_size to
0088 struct fpga_image_info. Before parse_header call, header_size is initialized
0089 with initial_header_size. If flag skip_header of fpga_manager_ops is true,
0090 .write function will get image buffer starting at header_size offset from the
0091 beginning. If data_size is set, .write function will get data_size bytes of
0092 the image buffer, otherwise .write will get data up to the end of image buffer.
0093 This will not affect .write_sg, .write_sg will still get whole image in
0094 sg_table form. If FPGA image is already mapped as a single contiguous buffer,
0095 whole buffer will be passed into .parse_header. If image is in scatter-gather
0096 form, core code will buffer up at least .initial_header_size before the first
0097 call of .parse_header, if it is not enough, .parse_header should set desired
0098 size into info->header_size and return -EAGAIN, then it will be called again
0099 with greater part of image buffer on the input.
0100 
0101 The .write_init function will prepare the FPGA to receive the image data. The
0102 buffer passed into .write_init will be at least info->header_size bytes long;
0103 if the whole bitstream is not immediately available then the core code will
0104 buffer up at least this much before starting.
0105 
0106 The .write function writes a buffer to the FPGA. The buffer may be contain the
0107 whole FPGA image or may be a smaller chunk of an FPGA image.  In the latter
0108 case, this function is called multiple times for successive chunks. This interface
0109 is suitable for drivers which use PIO.
0110 
0111 The .write_sg version behaves the same as .write except the input is a sg_table
0112 scatter list. This interface is suitable for drivers which use DMA.
0113 
0114 The .write_complete function is called after all the image has been written
0115 to put the FPGA into operating mode.
0116 
0117 The ops include a .state function which will determine the state the FPGA is in
0118 and return a code of type enum fpga_mgr_states.  It doesn't result in a change
0119 in state.
0120 
0121 API for implementing a new FPGA Manager driver
0122 ----------------------------------------------
0123 
0124 * ``fpga_mgr_states`` -  Values for :c:expr:`fpga_manager->state`.
0125 * struct fpga_manager -  the FPGA manager struct
0126 * struct fpga_manager_ops -  Low level FPGA manager driver ops
0127 * struct fpga_manager_info -  Parameter structure for fpga_mgr_register_full()
0128 * fpga_mgr_register_full() -  Create and register an FPGA manager using the
0129   fpga_mgr_info structure to provide the full flexibility of options
0130 * fpga_mgr_register() -  Create and register an FPGA manager using standard
0131   arguments
0132 * devm_fpga_mgr_register_full() -  Resource managed version of
0133   fpga_mgr_register_full()
0134 * devm_fpga_mgr_register() -  Resource managed version of fpga_mgr_register()
0135 * fpga_mgr_unregister() -  Unregister an FPGA manager
0136 
0137 .. kernel-doc:: include/linux/fpga/fpga-mgr.h
0138    :functions: fpga_mgr_states
0139 
0140 .. kernel-doc:: include/linux/fpga/fpga-mgr.h
0141    :functions: fpga_manager
0142 
0143 .. kernel-doc:: include/linux/fpga/fpga-mgr.h
0144    :functions: fpga_manager_ops
0145 
0146 .. kernel-doc:: include/linux/fpga/fpga-mgr.h
0147    :functions: fpga_manager_info
0148 
0149 .. kernel-doc:: drivers/fpga/fpga-mgr.c
0150    :functions: fpga_mgr_register_full
0151 
0152 .. kernel-doc:: drivers/fpga/fpga-mgr.c
0153    :functions: fpga_mgr_register
0154 
0155 .. kernel-doc:: drivers/fpga/fpga-mgr.c
0156    :functions: devm_fpga_mgr_register_full
0157 
0158 .. kernel-doc:: drivers/fpga/fpga-mgr.c
0159    :functions: devm_fpga_mgr_register
0160 
0161 .. kernel-doc:: drivers/fpga/fpga-mgr.c
0162    :functions: fpga_mgr_unregister