0001 d) Xilinx IP cores
0002
0003 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
0004 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
0005 of standard device types (network, serial, etc.) and miscellaneous
0006 devices (gpio, LCD, spi, etc). Also, since these devices are
0007 implemented within the fpga fabric every instance of the device can be
0008 synthesised with different options that change the behaviour.
0009
0010 Each IP-core has a set of parameters which the FPGA designer can use to
0011 control how the core is synthesized. Historically, the EDK tool would
0012 extract the device parameters relevant to device drivers and copy them
0013 into an 'xparameters.h' in the form of #define symbols. This tells the
0014 device drivers how the IP cores are configured, but it requires the kernel
0015 to be recompiled every time the FPGA bitstream is resynthesized.
0016
0017 The new approach is to export the parameters into the device tree and
0018 generate a new device tree each time the FPGA bitstream changes. The
0019 parameters which used to be exported as #defines will now become
0020 properties of the device node. In general, device nodes for IP-cores
0021 will take the following form:
0022
0023 (name): (generic-name)@(base-address) {
0024 compatible = "xlnx,(ip-core-name)-(HW_VER)"
0025 [, (list of compatible devices), ...];
0026 reg = <(baseaddr) (size)>;
0027 interrupt-parent = <&interrupt-controller-phandle>;
0028 interrupts = < ... >;
0029 xlnx,(parameter1) = "(string-value)";
0030 xlnx,(parameter2) = <(int-value)>;
0031 };
0032
0033 (generic-name): an open firmware-style name that describes the
0034 generic class of device. Preferably, this is one word, such
0035 as 'serial' or 'ethernet'.
0036 (ip-core-name): the name of the ip block (given after the BEGIN
0037 directive in system.mhs). Should be in lowercase
0038 and all underscores '_' converted to dashes '-'.
0039 (name): is derived from the "PARAMETER INSTANCE" value.
0040 (parameter#): C_* parameters from system.mhs. The C_ prefix is
0041 dropped from the parameter name, the name is converted
0042 to lowercase and all underscore '_' characters are
0043 converted to dashes '-'.
0044 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
0045 (HW_VER): from the HW_VER parameter.
0046 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
0047
0048 Typically, the compatible list will include the exact IP core version
0049 followed by an older IP core version which implements the same
0050 interface or any other device with the same interface.
0051
0052 'reg' and 'interrupts' are all optional properties.
0053
0054 For example, the following block from system.mhs:
0055
0056 BEGIN opb_uartlite
0057 PARAMETER INSTANCE = opb_uartlite_0
0058 PARAMETER HW_VER = 1.00.b
0059 PARAMETER C_BAUDRATE = 115200
0060 PARAMETER C_DATA_BITS = 8
0061 PARAMETER C_ODD_PARITY = 0
0062 PARAMETER C_USE_PARITY = 0
0063 PARAMETER C_CLK_FREQ = 50000000
0064 PARAMETER C_BASEADDR = 0xEC100000
0065 PARAMETER C_HIGHADDR = 0xEC10FFFF
0066 BUS_INTERFACE SOPB = opb_7
0067 PORT OPB_Clk = CLK_50MHz
0068 PORT Interrupt = opb_uartlite_0_Interrupt
0069 PORT RX = opb_uartlite_0_RX
0070 PORT TX = opb_uartlite_0_TX
0071 PORT OPB_Rst = sys_bus_reset_0
0072 END
0073
0074 becomes the following device tree node:
0075
0076 opb_uartlite_0: serial@ec100000 {
0077 device_type = "serial";
0078 compatible = "xlnx,opb-uartlite-1.00.b";
0079 reg = <ec100000 10000>;
0080 interrupt-parent = <&opb_intc_0>;
0081 interrupts = <1 0>; // got this from the opb_intc parameters
0082 current-speed = <d#115200>; // standard serial device prop
0083 clock-frequency = <d#50000000>; // standard serial device prop
0084 xlnx,data-bits = <8>;
0085 xlnx,odd-parity = <0>;
0086 xlnx,use-parity = <0>;
0087 };
0088
0089 That covers the general approach to binding xilinx IP cores into the
0090 device tree. The following are bindings for specific devices:
0091
0092 i) Xilinx ML300 Framebuffer
0093
0094 Simple framebuffer device from the ML300 reference design (also on the
0095 ML403 reference design as well as others).
0096
0097 Optional properties:
0098 - resolution = <xres yres> : pixel resolution of framebuffer. Some
0099 implementations use a different resolution.
0100 Default is <d#640 d#480>
0101 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
0102 Default is <d#1024 d#480>.
0103 - rotate-display (empty) : rotate display 180 degrees.
0104
0105 ii) Xilinx SystemACE
0106
0107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
0108 bitstream stored on a CF card. It can also be used as a generic CF
0109 interface device.
0110
0111 Optional properties:
0112 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
0113
0114 iii) Xilinx EMAC and Xilinx TEMAC
0115
0116 Xilinx Ethernet devices. In addition to general xilinx properties
0117 listed above, nodes for these devices should include a phy-handle
0118 property, and may include other common network device properties
0119 like local-mac-address.
0120
0121 iv) Xilinx Uartlite
0122
0123 Xilinx uartlite devices are simple fixed speed serial ports.
0124
0125 Required properties:
0126 - current-speed : Baud rate of uartlite
0127
0128 v) Xilinx hwicap
0129
0130 Xilinx hwicap devices provide access to the configuration logic
0131 of the FPGA through the Internal Configuration Access Port
0132 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
0133 readback of the configuration information, and some control over
0134 'warm boots' of the FPGA fabric.
0135
0136 Required properties:
0137 - xlnx,family : The family of the FPGA, necessary since the
0138 capabilities of the underlying ICAP hardware
0139 differ between different families. May be
0140 'virtex2p', 'virtex4', or 'virtex5'.
0141 - compatible : should contain "xlnx,xps-hwicap-1.00.a" or
0142 "xlnx,opb-hwicap-1.00.b".
0143
0144 vi) Xilinx Uart 16550
0145
0146 Xilinx UART 16550 devices are very similar to the NS16550 but with
0147 different register spacing and an offset from the base address.
0148
0149 Required properties:
0150 - clock-frequency : Frequency of the clock input
0151 - reg-offset : A value of 3 is required
0152 - reg-shift : A value of 2 is required
0153
0154 vii) Xilinx USB Host controller
0155
0156 The Xilinx USB host controller is EHCI compatible but with a different
0157 base address for the EHCI registers, and it is always a big-endian
0158 USB Host controller. The hardware can be configured as high speed only,
0159 or high speed/full speed hybrid.
0160
0161 Required properties:
0162 - xlnx,support-usb-fs: A value 0 means the core is built as high speed
0163 only. A value 1 means the core also supports
0164 full speed devices.
0165
