0001 CE4100 Device Tree Bindings
0002 ---------------------------
0003
0004 The CE4100 SoC uses for in core peripherals the following compatible
0005 format: <vendor>,<chip>-<device>.
0006 Many of the "generic" devices like HPET or IO APIC have the ce4100
0007 name in their compatible property because they first appeared in this
0008 SoC.
0009
0010 The CPU nodes
0011 -------------
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016
0017 cpu@0 {
0018 device_type = "cpu";
0019 compatible = "intel,ce4100";
0020 reg = <0x00>;
0021 };
0022
0023 cpu@2 {
0024 device_type = "cpu";
0025 compatible = "intel,ce4100";
0026 reg = <0x02>;
0027 };
0028 };
0029
0030 A "cpu" node describes one logical processor (hardware thread).
0031
0032 Required properties:
0033
0034 - device_type
0035 Device type, must be "cpu".
0036
0037 - reg
0038 Local APIC ID, the unique number assigned to each processor by
0039 system hardware.
0040
0041 The SoC node
0042 ------------
0043
0044 This node describes the in-core peripherals. Required property:
0045 compatible = "intel,ce4100-cp";
0046
0047 The PCI node
0048 ------------
0049 This node describes the PCI bus on the SoC. Its property should be
0050 compatible = "intel,ce4100-pci", "pci";
0051
0052 If the OS is using the IO-APIC for interrupt routing then the reported
0053 interrupt numbers for devices is no longer true. In order to obtain the
0054 correct interrupt number, the child node which represents the device has
0055 to contain the interrupt property. Besides the interrupt property it has
0056 to contain at least the reg property containing the PCI bus address and
0057 compatible property according to "PCI Bus Binding Revision 2.1".
