0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
0008
0009 maintainers:
0010 - Roger Quadros <rogerq@kernel.org>
0011
0012 properties:
0013 compatible:
0014 oneOf:
0015 - const: ti,j721e-usb
0016 - const: ti,am64-usb
0017 - items:
0018 - const: ti,j721e-usb
0019 - const: ti,am64-usb
0020
0021 reg:
0022 maxItems: 1
0023
0024 ranges: true
0025
0026 power-domains:
0027 description:
0028 PM domain provider node and an args specifier containing
0029 the USB device id value. See,
0030 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
0031 maxItems: 1
0032
0033 clocks:
0034 description: Clock phandles to usb2_refclk and lpm_clk
0035 minItems: 2
0036 maxItems: 2
0037
0038 clock-names:
0039 items:
0040 - const: ref
0041 - const: lpm
0042
0043 ti,usb2-only:
0044 description:
0045 If present, it restricts the controller to USB2.0 mode of
0046 operation. Must be present if USB3 PHY is not available
0047 for USB.
0048 type: boolean
0049
0050 ti,vbus-divider:
0051 description:
0052 Should be present if USB VBUS line is connected to the
0053 VBUS pin of the SoC via a 1/3 voltage divider.
0054 type: boolean
0055
0056 assigned-clocks:
0057 maxItems: 1
0058
0059 assigned-clock-parents:
0060 maxItems: 1
0061
0062 '#address-cells':
0063 const: 2
0064
0065 '#size-cells':
0066 const: 2
0067
0068 dma-coherent: true
0069
0070 patternProperties:
0071 "^usb@":
0072 type: object
0073
0074 required:
0075 - compatible
0076 - reg
0077 - power-domains
0078 - clocks
0079 - clock-names
0080
0081 additionalProperties: false
0082
0083 examples:
0084 - |
0085 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0086 #include <dt-bindings/interrupt-controller/arm-gic.h>
0087
0088 bus {
0089 #address-cells = <2>;
0090 #size-cells = <2>;
0091
0092 cdns_usb@4104000 {
0093 compatible = "ti,j721e-usb";
0094 reg = <0x00 0x4104000 0x00 0x100>;
0095 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
0096 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
0097 clock-names = "ref", "lpm";
0098 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
0099 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
0100 #address-cells = <2>;
0101 #size-cells = <2>;
0102
0103 usb@6000000 {
0104 compatible = "cdns,usb3";
0105 reg = <0x00 0x6000000 0x00 0x10000>,
0106 <0x00 0x6010000 0x00 0x10000>,
0107 <0x00 0x6020000 0x00 0x10000>;
0108 reg-names = "otg", "xhci", "dev";
0109 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
0110 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
0111 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
0112 interrupt-names = "host",
0113 "peripheral",
0114 "otg";
0115 maximum-speed = "super-speed";
0116 dr_mode = "otg";
0117 };
0118 };
0119 };
