bindings/usb/rockchip%2Cdwc3.yaml

0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip SuperSpeed DWC3 USB SoC controller
0008
0009 maintainers:
0010   - Heiko Stuebner <heiko@sntech.de>
0011
0012 description:
0013   The common content of the node is defined in snps,dwc3.yaml.
0014
0015   Phy documentation is provided in the following places.
0016
0017   USB2.0 PHY
0018   Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
0019
0020   Type-C PHY
0021   Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
0022
0023 allOf:
0024   - $ref: snps,dwc3.yaml#
0025
0026 select:
0027   properties:
0028     compatible:
0029       contains:
0030         enum:
0031           - rockchip,rk3328-dwc3
0032           - rockchip,rk3399-dwc3
0033           - rockchip,rk3568-dwc3
0034   required:
0035     - compatible
0036
0037 properties:
0038   compatible:
0039     items:
0040       - enum:
0041           - rockchip,rk3328-dwc3
0042           - rockchip,rk3399-dwc3
0043           - rockchip,rk3568-dwc3
0044       - const: snps,dwc3
0045
0046   reg:
0047     maxItems: 1
0048
0049   interrupts:
0050     maxItems: 1
0051
0052   clocks:
0053     minItems: 3
0054     items:
0055       - description:
0056           Controller reference clock, must to be 24 MHz
0057       - description:
0058           Controller suspend clock, must to be 24 MHz or 32 KHz
0059       - description:
0060           Master/Core clock, must to be >= 62.5 MHz for SS
0061           operation and >= 30MHz for HS operation
0062       - description:
0063           Controller grf clock
0064
0065   clock-names:
0066     minItems: 3
0067     items:
0068       - const: ref_clk
0069       - const: suspend_clk
0070       - const: bus_clk
0071       - const: grf_clk
0072
0073   power-domains:
0074     maxItems: 1
0075
0076   resets:
0077     maxItems: 1
0078
0079   reset-names:
0080     const: usb3-otg
0081
0082 unevaluatedProperties: false
0083
0084 required:
0085   - compatible
0086   - reg
0087   - interrupts
0088   - clocks
0089   - clock-names
0090
0091 examples:
0092   - |
0093     #include <dt-bindings/clock/rk3399-cru.h>
0094     #include <dt-bindings/interrupt-controller/arm-gic.h>
0095
0096     bus {
0097       #address-cells = <2>;
0098       #size-cells = <2>;
0099
0100       usbdrd3_0: usb@fe800000 {
0101         compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
0102         reg = <0x0 0xfe800000 0x0 0x100000>;
0103         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0104         clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
0105                  <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
0106         clock-names = "ref_clk", "suspend_clk",
0107                       "bus_clk", "grf_clk";
0108         dr_mode = "otg";
0109       };
0110     };