0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (c) 2020 NXP
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: NXP iMX8MP Soc USB Controller
0009
0010 maintainers:
0011 - Li Jun <jun.li@nxp.com>
0012
0013 properties:
0014 compatible:
0015 const: fsl,imx8mp-dwc3
0016
0017 reg:
0018 items:
0019 - description: Address and length of the register set for HSIO Block Control
0020 - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
0021
0022 "#address-cells":
0023 enum: [ 1, 2 ]
0024
0025 "#size-cells":
0026 enum: [ 1, 2 ]
0027
0028 dma-ranges:
0029 description:
0030 See section 2.3.9 of the DeviceTree Specification.
0031
0032 ranges: true
0033
0034 interrupts:
0035 maxItems: 1
0036 description: The interrupt that is asserted when a wakeup event is
0037 received.
0038
0039 clocks:
0040 description:
0041 A list of phandle and clock-specifier pairs for the clocks
0042 listed in clock-names.
0043 items:
0044 - description: system hsio root clock.
0045 - description: suspend clock, used for usb wakeup logic.
0046
0047 clock-names:
0048 items:
0049 - const: hsio
0050 - const: suspend
0051
0052 fsl,permanently-attached:
0053 type: boolean
0054 description:
0055 Indicates if the device atached to a downstream port is
0056 permanently attached.
0057
0058 fsl,disable-port-power-control:
0059 type: boolean
0060 description:
0061 Indicates whether the host controller implementation includes port
0062 power control. Defines Bit 3 in capability register (HCCPARAMS).
0063
0064 fsl,over-current-active-low:
0065 type: boolean
0066 description:
0067 Over current signal polarity is active low.
0068
0069 fsl,power-active-low:
0070 type: boolean
0071 description:
0072 Power pad (PWR) polarity is active low.
0073
0074 # Required child node:
0075
0076 patternProperties:
0077 "^usb@[0-9a-f]+$":
0078 $ref: snps,dwc3.yaml#
0079
0080 required:
0081 - compatible
0082 - reg
0083 - "#address-cells"
0084 - "#size-cells"
0085 - dma-ranges
0086 - ranges
0087 - clocks
0088 - clock-names
0089 - interrupts
0090
0091 additionalProperties: false
0092
0093 examples:
0094 - |
0095 #include <dt-bindings/clock/imx8mp-clock.h>
0096 #include <dt-bindings/interrupt-controller/arm-gic.h>
0097 usb3_0: usb@32f10100 {
0098 compatible = "fsl,imx8mp-dwc3";
0099 reg = <0x32f10100 0x8>,
0100 <0x381f0000 0x20>;
0101 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
0102 <&clk IMX8MP_CLK_USB_ROOT>;
0103 clock-names = "hsio", "suspend";
0104 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0105 #address-cells = <1>;
0106 #size-cells = <1>;
0107 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
0108 ranges;
0109
0110 usb@38100000 {
0111 compatible = "snps,dwc3";
0112 reg = <0x38100000 0x10000>;
0113 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
0114 <&clk IMX8MP_CLK_USB_CORE_REF>,
0115 <&clk IMX8MP_CLK_USB_ROOT>;
0116 clock-names = "bus_early", "ref", "suspend";
0117 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
0118 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
0119 assigned-clock-rates = <500000000>;
0120 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0121 phys = <&usb3_phy0>, <&usb3_phy0>;
0122 phy-names = "usb2-phy", "usb3-phy";
0123 snps,dis-u2-freeclk-exists-quirk;
0124 };
0125 };
