bindings/usb/dwc3-xilinx.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx SuperSpeed DWC3 USB SoC controller
0008
0009 maintainers:
0010   - Manish Narani <manish.narani@xilinx.com>
0011
0012 properties:
0013   compatible:
0014     items:
0015       - enum:
0016           - xlnx,zynqmp-dwc3
0017           - xlnx,versal-dwc3
0018   reg:
0019     maxItems: 1
0020
0021   "#address-cells":
0022     enum: [ 1, 2 ]
0023
0024   "#size-cells":
0025     enum: [ 1, 2 ]
0026
0027   ranges: true
0028
0029   power-domains:
0030     description: specifies a phandle to PM domain provider node
0031     maxItems: 1
0032
0033   clocks:
0034     description:
0035       A list of phandle and clock-specifier pairs for the clocks
0036       listed in clock-names.
0037     items:
0038       - description: Master/Core clock, has to be >= 125 MHz
0039           for SS operation and >= 60MHz for HS operation.
0040       - description: Clock source to core during PHY power down.
0041
0042   clock-names:
0043     items:
0044       - const: bus_clk
0045       - const: ref_clk
0046
0047   resets:
0048     description:
0049       A list of phandles for resets listed in reset-names.
0050
0051     items:
0052       - description: USB core reset
0053       - description: USB hibernation reset
0054       - description: USB APB reset
0055
0056   reset-names:
0057     items:
0058       - const: usb_crst
0059       - const: usb_hibrst
0060       - const: usb_apbrst
0061
0062   phys:
0063     minItems: 1
0064     maxItems: 2
0065
0066   phy-names:
0067     minItems: 1
0068     maxItems: 2
0069     items:
0070       enum:
0071         - usb2-phy
0072         - usb3-phy
0073
0074   reset-gpios:
0075     description: GPIO used for the reset ulpi-phy
0076     maxItems: 1
0077
0078 # Required child node:
0079
0080 patternProperties:
0081   "^usb@[0-9a-f]+$":
0082     $ref: snps,dwc3.yaml#
0083
0084 required:
0085   - compatible
0086   - reg
0087   - "#address-cells"
0088   - "#size-cells"
0089   - ranges
0090   - power-domains
0091   - clocks
0092   - clock-names
0093   - resets
0094   - reset-names
0095
0096 additionalProperties: false
0097
0098 examples:
0099   - |
0100     #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
0101     #include <dt-bindings/power/xlnx-zynqmp-power.h>
0102     #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
0103     #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
0104     #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
0105     #include <dt-bindings/phy/phy.h>
0106     axi {
0107         #address-cells = <2>;
0108         #size-cells = <2>;
0109
0110         usb@0 {
0111             #address-cells = <0x2>;
0112             #size-cells = <0x2>;
0113             compatible = "xlnx,zynqmp-dwc3";
0114             reg = <0x0 0xff9d0000 0x0 0x100>;
0115             clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
0116             clock-names = "bus_clk", "ref_clk";
0117             power-domains = <&zynqmp_firmware PD_USB_0>;
0118             resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
0119                      <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
0120                      <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
0121             reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
0122             phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
0123             phy-names = "usb3-phy";
0124             ranges;
0125
0126             usb@fe200000 {
0127                 compatible = "snps,dwc3";
0128                 reg = <0x0 0xfe200000 0x0 0x40000>;
0129                 interrupt-names = "host", "otg";
0130                 interrupts = <0 65 4>, <0 69 4>;
0131                 dr_mode = "host";
0132                 dma-coherent;
0133             };
0134         };
0135     };