0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: TI J721e UFS Host Controller Glue Driver
0008
0009 maintainers:
0010 - Vignesh Raghavendra <vigneshr@ti.com>
0011
0012 properties:
0013 compatible:
0014 items:
0015 - const: ti,j721e-ufs
0016
0017 reg:
0018 maxItems: 1
0019 description: address of TI UFS glue registers
0020
0021 clocks:
0022 maxItems: 1
0023 description: phandle to the M-PHY clock
0024
0025 power-domains:
0026 maxItems: 1
0027
0028 assigned-clocks:
0029 maxItems: 1
0030
0031 assigned-clock-parents:
0032 maxItems: 1
0033
0034 "#address-cells":
0035 const: 2
0036
0037 "#size-cells":
0038 const: 2
0039
0040 ranges: true
0041
0042 required:
0043 - compatible
0044 - reg
0045 - clocks
0046 - power-domains
0047
0048 patternProperties:
0049 "^ufs@[0-9a-f]+$":
0050 $ref: cdns,ufshc.yaml
0051 description: |
0052 Cadence UFS controller node must be the child node.
0053 unevaluatedProperties: false
0054
0055 additionalProperties: false
0056
0057 examples:
0058 - |
0059 #include <dt-bindings/interrupt-controller/irq.h>
0060 #include <dt-bindings/interrupt-controller/arm-gic.h>
0061
0062 bus {
0063 #address-cells = <2>;
0064 #size-cells = <2>;
0065
0066 ufs-wrapper@4e80000 {
0067 compatible = "ti,j721e-ufs";
0068 reg = <0x0 0x4e80000 0x0 0x100>;
0069 power-domains = <&k3_pds 277>;
0070 clocks = <&k3_clks 277 1>;
0071 assigned-clocks = <&k3_clks 277 1>;
0072 assigned-clock-parents = <&k3_clks 277 4>;
0073
0074 ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
0075 #address-cells = <2>;
0076 #size-cells = <2>;
0077
0078 ufs@4000 {
0079 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
0080 reg = <0x0 0x4000 0x0 0x10000>;
0081 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0082 freq-table-hz = <19200000 19200000>;
0083 power-domains = <&k3_pds 277>;
0084 clocks = <&k3_clks 277 1>;
0085 assigned-clocks = <&k3_clks 277 1>;
0086 assigned-clock-parents = <&k3_clks 277 4>;
0087 clock-names = "core_clk";
0088 };
0089 };
0090 };
