0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung SoC series UFS host controller Device Tree Bindings
0008
0009 maintainers:
0010 - Alim Akhtar <alim.akhtar@samsung.com>
0011
0012 description: |
0013 Each Samsung UFS host controller instance should have its own node.
0014
0015 allOf:
0016 - $ref: ufs-common.yaml
0017
0018 properties:
0019 compatible:
0020 enum:
0021 - samsung,exynos7-ufs
0022 - samsung,exynosautov9-ufs
0023 - samsung,exynosautov9-ufs-vh
0024 - tesla,fsd-ufs
0025
0026 reg:
0027 items:
0028 - description: HCI register
0029 - description: vendor specific register
0030 - description: unipro register
0031 - description: UFS protector register
0032
0033 reg-names:
0034 items:
0035 - const: hci
0036 - const: vs_hci
0037 - const: unipro
0038 - const: ufsp
0039
0040 clocks:
0041 items:
0042 - description: ufs link core clock
0043 - description: unipro main clock
0044
0045 clock-names:
0046 items:
0047 - const: core_clk
0048 - const: sclk_unipro_main
0049
0050 phys:
0051 maxItems: 1
0052
0053 phy-names:
0054 const: ufs-phy
0055
0056 samsung,sysreg:
0057 $ref: '/schemas/types.yaml#/definitions/phandle-array'
0058 description: Should be phandle/offset pair. The phandle to the syscon node
0059 which indicates the FSYSx sysreg interface and the offset of
0060 the control register for UFS io coherency setting.
0061
0062 dma-coherent: true
0063
0064 required:
0065 - compatible
0066 - reg
0067 - phys
0068 - phy-names
0069 - clocks
0070 - clock-names
0071
0072 unevaluatedProperties: false
0073
0074 examples:
0075 - |
0076 #include <dt-bindings/interrupt-controller/arm-gic.h>
0077 #include <dt-bindings/clock/exynos7-clk.h>
0078
0079 ufs: ufs@15570000 {
0080 compatible = "samsung,exynos7-ufs";
0081 reg = <0x15570000 0x100>,
0082 <0x15570100 0x100>,
0083 <0x15571000 0x200>,
0084 <0x15572000 0x300>;
0085 reg-names = "hci", "vs_hci", "unipro", "ufsp";
0086 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0087 clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
0088 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
0089 clock-names = "core_clk", "sclk_unipro_main";
0090 pinctrl-names = "default";
0091 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
0092 phys = <&ufs_phy>;
0093 phy-names = "ufs-phy";
0094 };
0095 ...
