0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Universal Flash Storage (UFS) Controller
0008
0009 maintainers:
0010 - Bjorn Andersson <bjorn.andersson@linaro.org>
0011 - Andy Gross <agross@kernel.org>
0012
0013 # Select only our matches, not all jedec,ufs-2.0
0014 select:
0015 properties:
0016 compatible:
0017 contains:
0018 const: qcom,ufshc
0019 required:
0020 - compatible
0021
0022 properties:
0023 compatible:
0024 items:
0025 - enum:
0026 - qcom,msm8994-ufshc
0027 - qcom,msm8996-ufshc
0028 - qcom,msm8998-ufshc
0029 - qcom,sc8280xp-ufshc
0030 - qcom,sdm845-ufshc
0031 - qcom,sm6350-ufshc
0032 - qcom,sm8150-ufshc
0033 - qcom,sm8250-ufshc
0034 - qcom,sm8350-ufshc
0035 - qcom,sm8450-ufshc
0036 - const: qcom,ufshc
0037 - const: jedec,ufs-2.0
0038
0039 clocks:
0040 minItems: 8
0041 maxItems: 11
0042
0043 clock-names:
0044 minItems: 8
0045 maxItems: 11
0046
0047 interconnects:
0048 minItems: 2
0049 maxItems: 2
0050
0051 interconnect-names:
0052 items:
0053 - const: ufs-ddr
0054 - const: cpu-ufs
0055
0056 iommus:
0057 minItems: 1
0058 maxItems: 2
0059
0060 phys:
0061 maxItems: 1
0062
0063 phy-names:
0064 items:
0065 - const: ufsphy
0066
0067 power-domains:
0068 maxItems: 1
0069
0070 reg:
0071 minItems: 1
0072 maxItems: 2
0073
0074 resets:
0075 maxItems: 1
0076
0077 '#reset-cells':
0078 const: 1
0079
0080 reset-names:
0081 items:
0082 - const: rst
0083
0084 reset-gpios:
0085 maxItems: 1
0086 description:
0087 GPIO connected to the RESET pin of the UFS memory device.
0088
0089 required:
0090 - compatible
0091 - reg
0092
0093 allOf:
0094 - $ref: ufs-common.yaml
0095
0096 - if:
0097 properties:
0098 compatible:
0099 contains:
0100 enum:
0101 - qcom,msm8998-ufshc
0102 - qcom,sc8280xp-ufshc
0103 - qcom,sm8250-ufshc
0104 - qcom,sm8350-ufshc
0105 - qcom,sm8450-ufshc
0106 then:
0107 properties:
0108 clocks:
0109 minItems: 8
0110 maxItems: 8
0111 clock-names:
0112 items:
0113 - const: core_clk
0114 - const: bus_aggr_clk
0115 - const: iface_clk
0116 - const: core_clk_unipro
0117 - const: ref_clk
0118 - const: tx_lane0_sync_clk
0119 - const: rx_lane0_sync_clk
0120 - const: rx_lane1_sync_clk
0121 reg:
0122 minItems: 1
0123 maxItems: 1
0124
0125 - if:
0126 properties:
0127 compatible:
0128 contains:
0129 enum:
0130 - qcom,sdm845-ufshc
0131 - qcom,sm6350-ufshc
0132 - qcom,sm8150-ufshc
0133 then:
0134 properties:
0135 clocks:
0136 minItems: 9
0137 maxItems: 9
0138 clock-names:
0139 items:
0140 - const: core_clk
0141 - const: bus_aggr_clk
0142 - const: iface_clk
0143 - const: core_clk_unipro
0144 - const: ref_clk
0145 - const: tx_lane0_sync_clk
0146 - const: rx_lane0_sync_clk
0147 - const: rx_lane1_sync_clk
0148 - const: ice_core_clk
0149 reg:
0150 minItems: 2
0151 maxItems: 2
0152
0153 - if:
0154 properties:
0155 compatible:
0156 contains:
0157 enum:
0158 - qcom,msm8996-ufshc
0159 then:
0160 properties:
0161 clocks:
0162 minItems: 11
0163 maxItems: 11
0164 clock-names:
0165 items:
0166 - const: core_clk_src
0167 - const: core_clk
0168 - const: bus_clk
0169 - const: bus_aggr_clk
0170 - const: iface_clk
0171 - const: core_clk_unipro_src
0172 - const: core_clk_unipro
0173 - const: core_clk_ice
0174 - const: ref_clk
0175 - const: tx_lane0_sync_clk
0176 - const: rx_lane0_sync_clk
0177 reg:
0178 minItems: 1
0179 maxItems: 1
0180
0181 # TODO: define clock bindings for qcom,msm8994-ufshc
0182
0183 unevaluatedProperties: false
0184
0185 examples:
0186 - |
0187 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
0188 #include <dt-bindings/clock/qcom,rpmh.h>
0189 #include <dt-bindings/gpio/gpio.h>
0190 #include <dt-bindings/interconnect/qcom,sm8450.h>
0191 #include <dt-bindings/interrupt-controller/arm-gic.h>
0192
0193 soc {
0194 #address-cells = <2>;
0195 #size-cells = <2>;
0196
0197 ufs@1d84000 {
0198 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
0199 "jedec,ufs-2.0";
0200 reg = <0 0x01d84000 0 0x3000>;
0201 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
0202 phys = <&ufs_mem_phy_lanes>;
0203 phy-names = "ufsphy";
0204 lanes-per-direction = <2>;
0205 #reset-cells = <1>;
0206 resets = <&gcc GCC_UFS_PHY_BCR>;
0207 reset-names = "rst";
0208 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
0209
0210 vcc-supply = <&vreg_l7b_2p5>;
0211 vcc-max-microamp = <1100000>;
0212 vccq-supply = <&vreg_l9b_1p2>;
0213 vccq-max-microamp = <1200000>;
0214
0215 power-domains = <&gcc UFS_PHY_GDSC>;
0216 iommus = <&apps_smmu 0xe0 0x0>;
0217 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
0218 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
0219 interconnect-names = "ufs-ddr", "cpu-ufs";
0220
0221 clock-names = "core_clk",
0222 "bus_aggr_clk",
0223 "iface_clk",
0224 "core_clk_unipro",
0225 "ref_clk",
0226 "tx_lane0_sync_clk",
0227 "rx_lane0_sync_clk",
0228 "rx_lane1_sync_clk";
0229 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
0230 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
0231 <&gcc GCC_UFS_PHY_AHB_CLK>,
0232 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
0233 <&rpmhcc RPMH_CXO_CLK>,
0234 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
0235 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
0236 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
0237 freq-table-hz = <75000000 300000000>,
0238 <0 0>,
0239 <0 0>,
0240 <75000000 300000000>,
0241 <75000000 300000000>,
0242 <0 0>,
0243 <0 0>,
0244 <0 0>;
0245 };
0246 };
